On 1/29/23 16:03, LIU Zhiwei wrote:
Thanks. It's a bug. We should load all memory addresses to local TCG temps
first.
Do you think we should probe all the memory addresses for the store pair instructions? If
so, can we avoid the use of a helper function?
Depends on what the hardware does. Even with a trap in the middle the stores are
restartable, since no register state changes.
But if you'd like no changes verifying both stores, for this case you can pack the pair
into a larger data type: TCGv_i64 for pair of 32-bit, and TCGv_i128 for pair of 64-bit.
Patches for TCGv_i128 [1] are just finishing review; patches to describe atomicity of the
larger operation are also on list [2]. Anyway, the idea is that you issue one TCG memory
operation, the entire operation is validated, and then the stores happen.
The main reason is that assembler can do this check. Is it necessary to check
this in QEMU?
Yes. Conciser what happens when the insn is encoded with .long. Does the hardware trap
an illegal instruction? Is the behavior simply unspecified? The manual could be improved
to specify, akin to the Arm terms: UNDEFINED, CONSTRAINED UNPREDICTABLE, IMPLEMENTATION
DEFINED, etc.
r~
[1]
https://patchew.org/QEMU/20230126043824.54819-1-richard.hender...@linaro.org/
[2]
https://patchew.org/QEMU/20221118094754.242910-1-richard.hender...@linaro.org/
