> I'm adding a new target to qemu, now, I'm writing mmu simulation, but > it make me confused. > > When TLB miss occurred, I can't seperate DTLB miss from ITLB miss. > > I implemented it like this from target-xtensa: > > if (rw & 2) > HANDLE DTLB MISS > else > HANDLE ITLB MISS
I guess that you mean qemu softmmu tlb miss, that results in a call to the void tlb_fill(CPUState *env, target_ulong vaddr, int is_write, int mmu_idx, void *retaddr) 'is_write' argument meaning in this call is the following: 0 -- data read, 1 -- data write, 2 -- instruction read. So, probably you should swap your DTLB and ITLB handlers. > But it didn't work. May I have some suggestions? -- Thanks. -- Max
