Hi All: This series tries to introduce PASID support for Intel IOMMU. The work is based on the previous scalabe mode support by implement the ECAP_PASID. A new "x-pasid-mode" is introduced to enable this mode. All internal vIOMMU codes were extended to support PASID instead of the current RID2PASID method. The code is also capable of provisiong address space with PASID. Note that no devices can issue PASID DMA right now, this needs future work.
This will be used for prototying PASID based device like virtio or future vPASID support for Intel IOMMU. Test has been done with the Linux guest with scalalbe mode enabled and disabled. A virtio prototype[1][2] that can issue PAISD based DMA request were also tested, different PASID were used in TX and RX in those testing drivers. Changes since V2: - use PCI_BUILD_BDF() instead of vtd_make_source_id() - Tweak the comments above vtd_as_hash() - use PCI_BUS_NUM() instead of open coding - rename vtd_as to vtd_address_spaces - rename vtd_qualify_report_fault() to vtd_report_qualify_fault() - forbid device-iotlb with PASID - report PASID based qualified fault - log PASID during errors Changes since V1: - speed up IOMMU translation when RID2PASID is not used - remove the unnecessary L1 PASID invalidation descriptor support - adding support for cacthing the translation to interrupt range when in the case of PT and scalable mode - refine the comments to explain the hash algorithm used in IOTLB lookups Please review. [1] https://github.com/jasowang/qemu.git virtio-pasid [2] https://github.com/jasowang/linux.git virtio-pasid Jason Wang (4): intel-iommu: don't warn guest errors when getting rid2pasid entry intel-iommu: drop VTDBus intel-iommu: convert VTD_PE_GET_FPD_ERR() to be a function intel-iommu: PASID support hw/i386/intel_iommu.c | 685 ++++++++++++++++++++++----------- hw/i386/intel_iommu_internal.h | 16 +- hw/i386/trace-events | 2 + include/hw/i386/intel_iommu.h | 18 +- include/hw/pci/pci_bus.h | 2 + 5 files changed, 482 insertions(+), 241 deletions(-) -- 2.25.1
