As the Cortex A7 MPCore Technical reference says :
"When FPU option is selected without NEON, the FPU is VFPv4-D16 and
uses 16 double-precision registers. When the FPU is implemented with
NEON, the FPU is VFPv4-D32 and uses 32 double-precision registers.
This register bank is shared with NEON."
Modify the mvfr0 register value of the cortex A7 to advertise only 16
registers when NEON is not available, and not 32 registers.
Signed-off-by: Cédric Le Goater <c...@kaod.org>
---
target/arm/cpu.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 7ec3281da9aa..01dc74c32add 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1684,6 +1684,10 @@ static void arm_cpu_realizefn(DeviceState *dev, Error
**errp)
cpu->isar.id_isar6 = u;
if (!arm_feature(env, ARM_FEATURE_M)) {
+ u = cpu->isar.mvfr0;
+ u = FIELD_DP32(u, MVFR0, SIMDREG, 1); /* 16 registers */
+ cpu->isar.mvfr0 = u;
+
u = cpu->isar.mvfr1;
u = FIELD_DP32(u, MVFR1, SIMDLS, 0);
u = FIELD_DP32(u, MVFR1, SIMDINT, 0);
--
2.37.3
