On 8/29/22 19:11, Ricky Zhou wrote:
Many instructions which load/store 128-bit values are supposed to
raise #GP when the memory operand isn't 16-byte aligned. This includes:
- Instructions explicitly requiring memory alignment (Exceptions Type 1
in the "AVX and SSE Instruction Exception Specification" section of
the SDM)
- Legacy SSE instructions that load/store 128-bit values (Exceptions
Types 2 and 4).
This change sets MO_ALIGN_16 on 128-bit memory accesses that require
16-byte alignment. It adds cpu_record_sigbus and cpu_do_unaligned_access
handlers that simulate a #GP exception in qemu-user and qemu-system,
respectively.
One minor behavior change apart from what is described above: Prior to
this change, emulation of cvttps2pi and cvtps2pi instructions would
incorrectly read 16 bytes of memory instead of 8. I double-checked on
real hardware that these instructions only read 8 bytes (and do not have
any address alignment requirements).
This should really be split out to a separate patch.
@@ -3621,7 +3629,11 @@ static void gen_sse(CPUX86State *env, DisasContext *s,
int b,
if (mod != 3) {
gen_lea_modrm(env, s, modrm);
op2_offset = offsetof(CPUX86State,xmm_t0);
- gen_ldo_env_A0(s, op2_offset);
+ if ((b >> 8) & 1) {
Aka b1.
Otherwise,
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
r~
