Previously sent as patches 43-45 of [PATCH v10 00/45] CXl 2.0 emulation Support https://lore.kernel.org/qemu-devel/20220429144110.25167-45-jonathan.came...@huawei.com/#r
Now the initial CXL support is upstream, patch sets applying to different parts of the CXL infrastructure can be reviewed / applied in any order. I have just sent out arm/virt support and aim to send out DOE/CDAT patches shortly. This series is independent of those others. Changes since v10: - Rebase. - Typo fix in comment about xio3110. This series adds CXL switch support in the form of upstream and downstream ports + the additions to the interleave decoder in cxl-host to enable us to interleave across the downstream switch ports. The PCI IDs used have been allocated against Huawei's Vendor ID for use for emulation of these devices only. Primary use for this support is for testing the Linux kernel stack. Note only 1 level of switching / switch based HDM interleave decoding is supported - consistent with typical CXL 2.0 systems. Interleaving may occur and any / some / all of: - Across multiple CXL host bridges (static setup via Fixed Memory Windows). - Across multiple root ports in a given CXL host bridge (dynamic config via CXL host bridge register space. - Across multiple downstream switch ports (this series). All comments welcome, Thanks, Jonathan Jonathan Cameron (3): pci-bridge/cxl_upstream: Add a CXL switch upstream port pci-bridge/cxl_downstream: Add a CXL switch downstream port docs/cxl: Add switch documentation docs/system/devices/cxl.rst | 88 +++++++++++- hw/cxl/cxl-host.c | 43 +++++- hw/pci-bridge/cxl_downstream.c | 249 +++++++++++++++++++++++++++++++++ hw/pci-bridge/cxl_upstream.c | 216 ++++++++++++++++++++++++++++ hw/pci-bridge/meson.build | 2 +- include/hw/cxl/cxl.h | 5 + 6 files changed, 598 insertions(+), 5 deletions(-) create mode 100644 hw/pci-bridge/cxl_downstream.c create mode 100644 hw/pci-bridge/cxl_upstream.c -- 2.32.0
