On Mon, Dec 12, 2011 at 12:28 PM, Pawel Moll <pawel.m...@arm.com> wrote: > On Mon, 2011-12-12 at 12:14 +0000, Stefan Hajnoczi wrote: >> I noticed the virtio-mmio spec has an interrupt status register. On >> x86 and virtio-pci things are moving towards Message Signalled >> Interrupts and virtqueues having their own interrupts for better >> performance and flexibility. Any thoughts on how 1 interrupt per >> virtqueue works for virtio-mmio? > > This could be done by either creating devices with more then one > interrupt (platform device can take any number of resources) and > declaring that first queue uses the first one etc. > >> My feeling is that the interrupt details are board-specific and can't >> be described in virtio-mmio, > > It's just the the "design pattern" in the "embedded world" that devices > usually have one interrupt output, shared between its internal > functions. And - of course - there is no in-band signalling (like MSI) > possible - interrupt lines are just "wires" :-) In a boundary case > scenario we may face a situation when total amount of interrupts for all > queues may actually exceed amount of interrupt inputs available in the > interrupt controller... > > There may be a half-way solution - one interrupt per device but the > "active" queue number notified via the interrupt status register (as a > FIFO) so the driver wouldn't have to enumerate all the queues.
If there aren't already then pretty soon ARM-based systems will deal with PCIe and Message Signalled Interrupts. Are you sure new ARM boards are constraints to a small number of physical interrupts? Stefan
