I noticed the virtio-mmio spec has an interrupt status register. On x86 and virtio-pci things are moving towards Message Signalled Interrupts and virtqueues having their own interrupts for better performance and flexibility. Any thoughts on how 1 interrupt per virtqueue works for virtio-mmio?
My feeling is that the interrupt details are board-specific and can't be described in virtio-mmio, but it still jumped out at me that it looks like you're only thinking of 1 interrupt for the device. Stefan
