Hi Pavel,
On 9/6/22 10:23, Pavel Dovgalyuk wrote:
This patch adds Cavium Octeon vCPU for providing
Octeon-specific instructions.
Signed-off-by: Pavel Dovgalyuk <pavel.dovgal...@ispras.ru>
--
v2 changes:
- vCPU name changed to Octeon68XX (suggested by Richard Henderson)
---
target/mips/cpu-defs.c.inc | 28 ++++++++++++++++++++++++++++
target/mips/mips-defs.h | 1 +
2 files changed, 29 insertions(+)
diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc
index 582f940070..7f53c94ec8 100644
--- a/target/mips/cpu-defs.c.inc
+++ b/target/mips/cpu-defs.c.inc
@@ -921,6 +921,34 @@ const mips_def_t mips_defs[] =
.insn_flags = CPU_MIPS64R2 | ASE_DSP | ASE_DSP_R2,
.mmu_type = MMU_TYPE_R4000,
},
+ {
+ /*
+ * Octeon 68xx with MIPS64 Cavium Octeon features.
+ */
+ .name = "Octeon68XX",
+ .CP0_PRid = 0x000D9100,
+ .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
+ (MMU_TYPE_R4000 << CP0C0_MT),
+ .CP0_Config1 = MIPS_CONFIG1 | (0x3F << CP0C1_MMU) |
+ (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
+ (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
+ (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
+ .CP0_Config2 = MIPS_CONFIG2,
+ .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA) | (1 << CP0C3_DSPP) ,
+ .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) |
+ (0x3c << CP0C4_KScrExist) | (1U << CP0C4_MMUExtDef) |
+ (3U << CP0C4_MMUSizeExt),
+ .CP0_LLAddr_rw_bitmask = 0,
+ .CP0_LLAddr_shift = 4,
+ .CP0_PageGrain = (1 << CP0PG_ELPA),
+ .SYNCI_Step = 32,
+ .CCRes = 2,
+ .CP0_Status_rw_bitmask = 0x12F8FFFF,
+ .SEGBITS = 42,
+ .PABITS = 49,
+ .insn_flags = CPU_MIPS64R2 | INSN_OCTEON | ASE_DSP,
+ .mmu_type = MMU_TYPE_R4000,
+ },
#endif
};
^ This part should be the last patch of this series.
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index 0a12d982a7..a6cebe0265 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -42,6 +42,7 @@
#define INSN_LOONGSON2E 0x0000040000000000ULL
#define INSN_LOONGSON2F 0x0000080000000000ULL
#define INSN_LOONGSON3A 0x0000100000000000ULL
+#define INSN_OCTEON 0x0000200000000000ULL
/*
* bits 52-63: vendor-specific ASEs
*/
This hunk ^ belongs to the next patch, but I'd rather split patch #2,
first part being similar to commit 9d00539239 ("target/mips:
Introduce decodetree structure for NEC Vr54xx extension").
The series would look like:
target/mips: introduce decodetree structure for Cavium Octeon extension
target/mips: implement Octeon-specific BBIT instructions
target/mips: implement Octeon-specific arithmetic instructions
target/mips: add Cavium Octeon68XX CPU model
Regards,
Phil.
