On 6/9/22 21:26, Alistair Francis wrote:
From: Alistair Francis <alistair.fran...@wdc.com>
The following changes since commit 9cc1bf1ebca550f8d90f967ccd2b6d2e00e81387:
Merge tag 'pull-xen-20220609' of
https://xenbits.xen.org/git-http/people/aperard/qemu-dm into staging
(2022-06-09 08:25:17 -0700)
are available in the Git repository at:
g...@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20220610
for you to fetch changes up to 07314158f6aa4d2589520c194a7531b9364a8d54:
target/riscv: trans_rvv: Avoid assert for RV32 and e64 (2022-06-10 09:42:12
+1000)
----------------------------------------------------------------
Fourth RISC-V PR for QEMU 7.1
* Update MAINTAINERS
* Add support for Zmmul extension
* Fixup FDT errors when supplying device tree from the command line for virt
machine
* Avoid overflowing the addr_config buffer in the SiFive PLIC
* Support -device loader addresses above 2GB
* Correctly wake from WFI on VS-level external interrupts
* Fixes for RV128 support
* Support Vector extension tail agnostic setting elements' bits to all 1s
* Don't expose the CPU properties on named CPUs
* Fix vector extension assert for RV32
Applied, thanks. Please update https://wiki.qemu.org/ChangeLog/7.1 as
appropriate.
r~
----------------------------------------------------------------
Alistair Francis (4):
MAINTAINERS: Cover hw/core/uboot_image.h within Generic Loader section
hw/intc: sifive_plic: Avoid overflowing the addr_config buffer
target/riscv: Don't expose the CPU properties on names CPUs
target/riscv: trans_rvv: Avoid assert for RV32 and e64
Andrew Bresticker (1):
target/riscv: Wake on VS-level external interrupts
Atish Patra (1):
hw/riscv: virt: Generate fw_cfg DT node correctly
Frédéric Pétrot (1):
target/riscv/debug.c: keep experimental rv128 support working
Jamie Iles (1):
hw/core/loader: return image sizes as ssize_t
Weiwei Li (1):
target/riscv: add support for zmmul extension v0.1
eopXD (16):
target/riscv: rvv: Prune redundant ESZ, DSZ parameter passed
target/riscv: rvv: Prune redundant access_type parameter passed
target/riscv: rvv: Rename ambiguous esz
target/riscv: rvv: Early exit when vstart >= vl
target/riscv: rvv: Add tail agnostic for vv instructions
target/riscv: rvv: Add tail agnostic for vector load / store instructions
target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions
target/riscv: rvv: Add tail agnostic for vector integer shift
instructions
target/riscv: rvv: Add tail agnostic for vector integer comparison
instructions
target/riscv: rvv: Add tail agnostic for vector integer merge and move
instructions
target/riscv: rvv: Add tail agnostic for vector fix-point arithmetic
instructions
target/riscv: rvv: Add tail agnostic for vector floating-point
instructions
target/riscv: rvv: Add tail agnostic for vector reduction instructions
target/riscv: rvv: Add tail agnostic for vector mask instructions
target/riscv: rvv: Add tail agnostic for vector permutation instructions
target/riscv: rvv: Add option 'rvv_ta_all_1s' to enable optional tail
agnostic behavior
include/hw/loader.h | 55 +-
target/riscv/cpu.h | 4 +
target/riscv/internals.h | 6 +-
hw/arm/armv7m.c | 2 +-
hw/arm/boot.c | 8 +-
hw/core/generic-loader.c | 2 +-
hw/core/loader.c | 81 +-
hw/i386/x86.c | 2 +-
hw/intc/sifive_plic.c | 19 +-
hw/riscv/boot.c | 5 +-
hw/riscv/virt.c | 28 +-
target/riscv/cpu.c | 68 +-
target/riscv/cpu_helper.c | 4 +-
target/riscv/debug.c | 2 +
target/riscv/translate.c | 4 +
target/riscv/vector_helper.c | 1588 +++++++++++++++++++------------
target/riscv/insn_trans/trans_rvm.c.inc | 18 +-
target/riscv/insn_trans/trans_rvv.c.inc | 106 ++-
MAINTAINERS | 1 +
19 files changed, 1244 insertions(+), 759 deletions(-)
