On Wed, May 11, 2022 at 7:46 AM Anup Patel <apa...@ventanamicro.com> wrote:
>
> The mcountinhibit CSR is mandatory for priv spec v1.11 or higher. For
> implementation that don't want to implement can simply have a dummy
> mcountinhibit which always zero.
>
> Fixes: a4b2fa433125 ("target/riscv: Introduce privilege version field in
> the CSR ops.")
> Signed-off-by: Anup Patel <apa...@ventanamicro.com>
> Reviewed-by: Frank Chang <frank.ch...@sifive.com>
> Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
> ---
> target/riscv/cpu_bits.h | 3 +++
> target/riscv/csr.c | 2 ++
> 2 files changed, 5 insertions(+)
>
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index 4d04b20d06..4a55c6a709 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -159,6 +159,9 @@
> #define CSR_MTVEC 0x305
> #define CSR_MCOUNTEREN 0x306
>
> +/* Machine Counter Setup */
> +#define CSR_MCOUNTINHIBIT 0x320
> +
> /* 32-bit only */
> #define CSR_MSTATUSH 0x310
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 2bf0a97196..e144ce7135 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -3391,6 +3391,8 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> [CSR_MIE] = { "mie", any, NULL, NULL, rmw_mie
> },
> [CSR_MTVEC] = { "mtvec", any, read_mtvec, write_mtvec
> },
> [CSR_MCOUNTEREN] = { "mcounteren", any, read_mcounteren,
> write_mcounteren },
> + [CSR_MCOUNTINHIBIT] = { "mcountinhibit", any, read_zero, write_ignore,
> + .min_priv_ver =
> PRIV_VERSION_1_11_0 },
>
> [CSR_MSTATUSH] = { "mstatush", any32, read_mstatush,
> write_mstatush },
>
> --
> 2.34.1
>
Just to clarify, this is only required if this series is merged before
the PMU series.
FWIW,
Reviewed-by: Atish Patra <ati...@rivosinc.com>
--
Regards,
Atish
