Re: [PATCH v2 4/5] target/riscv: Add stimecmp support

[Richard Henderson]

On 4/26/22 16:08, Atish Patra wrote:

+static RISCVException write_stimecmp(CPURISCVState *env, int csrno,
+                                    target_ulong val)
+{
+    RISCVCPU *cpu = env_archcpu(env);
+
+    if (riscv_cpu_mxl(env) == MXL_RV32) {
+        uint64_t stimecmp_hi = env->stimecmp >> 32;
+        env->stimecmp = (stimecmp_hi << 32) | (val & 0xFFFFFFFF);
+    } else {
+        env->stimecmp = val;
+        riscv_timer_write_timecmp(cpu, env->stimer, env->stimecmp, 0, 
MIP_STIP);
+    }
+
+    return RISCV_EXCP_NONE;
+}
+
+static RISCVException write_stimecmph(CPURISCVState *env, int csrno,
+                                    target_ulong val)
+{
+    RISCVCPU *cpu = env_archcpu(env);
+    uint64_t timer_val = 0;
+
+    timer_val = (uint64_t)val << 32 | (env->stimecmp & 0xFFFFFFFF);
+    env->stimecmp = timer_val;
+    riscv_timer_write_timecmp(cpu, env->stimer, env->stimecmp, 0, MIP_STIP);
+
+    return RISCV_EXCP_NONE;
+}

Use deposit64() instead of open-coding the inserts.


r~