On Fri, Apr 1, 2022 at 11:00 PM Richard Henderson <richard.hender...@linaro.org> wrote: > > If an atomic operation fails on RISC-V, we want to generate > a store/amo fault and not a load fault. > > Annotate amo insns, so that we can recognize them after unwinding. > Transform the implementation access type to store/amo for reporting. > > > r~ > > > Richard Henderson (2): > target/riscv: Use cpu_loop_exit_restore directly from mmu faults > target/riscv: Mark amo insns during translation > > target/riscv/cpu.h | 15 ++++++ > target/riscv/cpu.c | 3 ++ > target/riscv/cpu_helper.c | 62 +++++++++++++++++-------- > target/riscv/translate.c | 9 ++++ > target/riscv/insn_trans/trans_rva.c.inc | 11 ++++- > 5 files changed, 79 insertions(+), 21 deletions(-)
Thanks! Applied to riscv-to-apply.next Alistair > > -- > 2.25.1 > >
