On Fri, Apr 1, 2022 at 11:01 PM Richard Henderson <richard.hender...@linaro.org> wrote: > > The riscv_raise_exception function stores its argument into > exception_index and then exits to the main loop. When we > have already set exception_index, we can just exit directly. > > Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> Alistair > --- > target/riscv/cpu_helper.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > index 1c60fb2e80..126251d5da 100644 > --- a/target/riscv/cpu_helper.c > +++ b/target/riscv/cpu_helper.c > @@ -1150,7 +1150,7 @@ void riscv_cpu_do_transaction_failed(CPUState *cs, > hwaddr physaddr, > env->badaddr = addr; > env->two_stage_lookup = riscv_cpu_virt_enabled(env) || > riscv_cpu_two_stage_lookup(mmu_idx); > - riscv_raise_exception(&cpu->env, cs->exception_index, retaddr); > + cpu_loop_exit_restore(cs, retaddr); > } > > void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, > @@ -1175,7 +1175,7 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr > addr, > env->badaddr = addr; > env->two_stage_lookup = riscv_cpu_virt_enabled(env) || > riscv_cpu_two_stage_lookup(mmu_idx); > - riscv_raise_exception(env, cs->exception_index, retaddr); > + cpu_loop_exit_restore(cs, retaddr); > } > > bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, > @@ -1311,7 +1311,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, > int size, > first_stage_error, > riscv_cpu_virt_enabled(env) || > riscv_cpu_two_stage_lookup(mmu_idx)); > - riscv_raise_exception(env, cs->exception_index, retaddr); > + cpu_loop_exit_restore(cs, retaddr); > } > > return true; > -- > 2.25.1 > >
