On Thu, 17 Mar 2022 at 05:55, Richard Henderson
<richard.hender...@linaro.org> wrote:
>
> Implement these out of line, so that tcg global temps
> (aka the architectural registers) are synced back to
> tcg storage as required. This makes sure that we get
> the proper results when status.PRS == status.CRS.
>
> Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
> +void helper_wrprs(CPUNios2State *env, uint32_t regno, uint32_t val)
> +{
> + unsigned prs = FIELD_EX32(env->ctrl[CR_STATUS], CR_STATUS, PRS);
> + env->shadow_regs[prs][regno] = val;
> +}
If we have the TB flag for "r0 is 0", then we'd need to make
wrprs writes to r0 in the current register set end the TB.
(If I'd been designing the ISA, I'd have made attempts to
use wrprs/rdprs with CRS == PRS cause an exception.)
Otherwise
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
thanks
-- PMM
