On 2/14/22 18:52, Daniel Henrique Barboza wrote:
On 2/14/22 14:34, Cédric Le Goater wrote:
On 2/11/22 19:33, Daniel Henrique Barboza wrote:
PPC_INTERRUPT_EBB is a new interrupt that will be used to deliver EBB
exceptions that had to be postponed because the thread wasn't in problem
state at the time the event-based branch was supposed to occur.
ISA 3.1 also defines two EBB exceptions: Performance Monitor EBB
exception and External EBB exception. They are being added as
POWERPC_EXCP_PERFM_EBB and POWERPC_EXCP_EXTERNAL_EBB.
PPC_INTERRUPT_EBB will check BESCR bits to see the EBB type that
occurred and trigger the appropriate exception. Both exceptions are
doing the same thing in this first implementation: clear BESCR_GE and
enter the branch with env->nip retrieved from SPR_EBBHR.
The checks being done by the interrupt code are msr_pr and BESCR_GE
states. All other checks (EBB facility check, BESCR_PME bit, specific
bits related to the event type) must be done beforehand.
Signed-off-by: Daniel Henrique Barboza <danielhb...@gmail.com>
It looks correct.
Reviewed-by: Cédric Le Goater <c...@kaod.org>
Next step is to modify the POWER9 input pins and these routines :
xive_tctx_realize()
xive_tctx_output()
power9_set_irq()
to add an EBB "wire" between the IC and the CPU.
Got it. I'll see if I can get this EBB lane up from the IC and CPU.
Any suggestions how I should test it?
Without a software stack configuring the IC and handling the EBB,
you can not.
C.
