On Thu, Jan 13, 2022 at 11:51 AM Weiwei Li <liwei...@iscas.ac.cn> wrote:
>
> Co-authored-by: ardxwe <ard...@gmail.com>
> Signed-off-by: Weiwei Li <liwei...@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqi...@iscas.ac.cn>
> Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 12 ++++++++++++
> target/riscv/cpu.h | 4 ++++
> target/riscv/translate.c | 8 ++++++++
> 3 files changed, 24 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 9bc25d3055..fc3ec5bca1 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -518,6 +518,11 @@ static void riscv_cpu_realize(DeviceState *dev, Error
> **errp)
> cpu->cfg.ext_d = true;
> }
>
> + if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx ||
> + cpu->cfg.ext_zhinxmin) {
> + cpu->cfg.ext_zfinx = true;
> + }
> +
> /* Set the ISA extensions, checks should have happened above */
> if (cpu->cfg.ext_i) {
> ext |= RVI;
> @@ -592,6 +597,13 @@ static void riscv_cpu_realize(DeviceState *dev, Error
> **errp)
> if (cpu->cfg.ext_j) {
> ext |= RVJ;
> }
> + if (cpu->cfg.ext_zfinx && ((ext & (RVF | RVD)) || cpu->cfg.ext_zfh ||
> + cpu->cfg.ext_zfhmin)) {
> + error_setg(errp,
> + "'Zfinx' cannot be supported together with 'F', 'D',
> 'Zfh',"
> + " 'Zfhmin'");
> + return;
> + }
>
> set_misa(env, env->misa_mxl, ext);
> }
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 4d63086765..b202bcbeff 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -327,8 +327,12 @@ struct RISCVCPU {
> bool ext_counters;
> bool ext_ifencei;
> bool ext_icsr;
> + bool ext_zdinx;
> bool ext_zfh;
> bool ext_zfhmin;
> + bool ext_zfinx;
> + bool ext_zhinx;
> + bool ext_zhinxmin;
>
> char *priv_spec;
> char *user_spec;
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 615048ec87..9687fa3e7c 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -77,8 +77,12 @@ typedef struct DisasContext {
> RISCVMXL ol;
> bool virt_enabled;
> bool ext_ifencei;
> + bool ext_zdinx;
> bool ext_zfh;
> bool ext_zfhmin;
> + bool ext_zfinx;
> + bool ext_zhinx;
> + bool ext_zhinxmin;
> bool hlsx;
> /* vector extension */
> bool vill;
> @@ -892,8 +896,12 @@ static void riscv_tr_init_disas_context(DisasContextBase
> *dcbase, CPUState *cs)
> ctx->misa_ext = env->misa_ext;
> ctx->frm = -1; /* unknown rounding mode */
> ctx->ext_ifencei = cpu->cfg.ext_ifencei;
> + ctx->ext_zdinx = cpu->cfg.ext_zdinx;
> ctx->ext_zfh = cpu->cfg.ext_zfh;
> ctx->ext_zfhmin = cpu->cfg.ext_zfhmin;
> + ctx->ext_zfinx = cpu->cfg.ext_zfinx;
> + ctx->ext_zhinx = cpu->cfg.ext_zhinx;
> + ctx->ext_zhinxmin = cpu->cfg.ext_zhinxmin;
> ctx->vlen = cpu->cfg.vlen;
> ctx->elen = cpu->cfg.elen;
> ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS);
> --
> 2.17.1
>
>
