On Sun, Jan 16, 2022 at 11:08 AM Weiwei Li <liwei...@iscas.ac.cn> wrote:
>
> - add PTE_PBMT bits: It uses two PTE bits, but otherwise has no effect on
> QEMU, since QEMU is sequentially consistent and doesn't model PMAs currently
> - add PTE_PBMT bits check for inner PTE
> - add reserved bits check for all PTE
>
> Signed-off-by: Weiwei Li <liwei...@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqi...@iscas.ac.cn>
> Tested-by: Heiko Stuebner <he...@sntech.de>
> Reviewed-by: Anup Patel <a...@brainfault.org>
> ---
> target/riscv/cpu.c | 1 +
> target/riscv/cpu.h | 1 +
> target/riscv/cpu_bits.h | 3 +++
> target/riscv/cpu_helper.c | 8 ++++++--
> 4 files changed, 11 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 45ac98e06b..4f82bd00a3 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -670,6 +670,7 @@ static Property riscv_cpu_properties[] = {
>
> DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
> DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
> + DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false),
>
> DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
> DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index c3d1845ca1..53f314c752 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -329,6 +329,7 @@ struct RISCVCPU {
> bool ext_icsr;
> bool ext_svinval;
> bool ext_svnapot;
> + bool ext_svpbmt;
> bool ext_zfh;
> bool ext_zfhmin;
>
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index bc23e3b523..ee294c1d0b 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -486,7 +486,10 @@ typedef enum {
> #define PTE_A 0x040 /* Accessed */
> #define PTE_D 0x080 /* Dirty */
> #define PTE_SOFT 0x300 /* Reserved for Software */
> +#define PTE_RSVD 0x1FC0000000000000 /* Reserved for future use */
> +#define PTE_PBMT 0x6000000000000000 /* Page-based memory types */
> #define PTE_N 0x8000000000000000 /* NAPOT translation */
> +#define PTE_ATTR 0xFFC0000000000000 /* All attributes bits */
>
> /* Page table PPN shift amount */
> #define PTE_PPN_SHIFT 10
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 832a2dd79c..f90766e026 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -619,17 +619,21 @@ restart:
> return TRANSLATE_FAIL;
> }
>
> - hwaddr ppn = (pte & ~(target_ulong)PTE_N) >> PTE_PPN_SHIFT;
> + hwaddr ppn = (pte & ~(target_ulong)PTE_ATTR) >> PTE_PPN_SHIFT;
This would break rv32. Please ref:
https://lore.kernel.org/qemu-devel/1569456861-8502-1-git-send-email-guo...@kernel.org/
>
> RISCVCPU *cpu = env_archcpu(env);
> if (!cpu->cfg.ext_svnapot && (pte & PTE_N)) {
> return TRANSLATE_FAIL;
> + } else if (!cpu->cfg.ext_svpbmt && (pte & PTE_PBMT)) {
> + return TRANSLATE_FAIL;
> + } else if (pte & PTE_RSVD) {
> + return TRANSLATE_FAIL;
> } else if (!(pte & PTE_V)) {
> /* Invalid PTE */
> return TRANSLATE_FAIL;
> } else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
> /* Inner PTE, continue walking */
> - if (pte & (PTE_D | PTE_A | PTE_U | PTE_N)) {
> + if (pte & (PTE_D | PTE_A | PTE_U | PTE_N | PTE_PBMT)) {
> return TRANSLATE_FAIL;
> }
> base = ppn << PGSHIFT;
> --
> 2.17.1
>
>
--
Best Regards
Guo Ren
ML: https://lore.kernel.org/linux-csky/
