Hi, In this new version the concept of PMUEvent was removed. We're now using only the PMUEventType enum and retrieving it on demand via a new helper called getPMUEventType. This also means that we're not trapping MMCR1 writes.
Changes from v4: - patches 1-4 from v4: already upstream - former patch 6 (initialize PMUEvents on MMCR1 write): removed - patch 1 (former 6): * removed PMUEvent type * overflow timers are back to CPUPPCState - patch 2 (former 7): * added a new getPMUEventType() function - other patches were changed to accomodate the changes in patch 1 and 2 - v4 link: https://lists.gnu.org/archive/html/qemu-devel/2021-10/msg03710.html Daniel Henrique Barboza (9): target/ppc: introduce PMUEventType and PMU overflow timers target/ppc: PMU basic cycle count for pseries TCG target/ppc: enable PMU counter overflow with cycle events target/ppc: enable PMU instruction count target/ppc/power8-pmu.c: add PM_RUN_INST_CMPL (0xFA) event target/ppc: PMU: handle setting of PMCs while running target/ppc/power8-pmu.c: handle overflow bits when PMU is running PPC64/TCG: Implement 'rfebb' instruction target/ppc/excp_helper.c: EBB handling adjustments Gustavo Romero (1): target/ppc: PMU Event-Based exception support hw/ppc/spapr_cpu_core.c | 6 + target/ppc/cpu.h | 60 +++- target/ppc/cpu_init.c | 20 +- target/ppc/excp_helper.c | 92 ++++++ target/ppc/helper.h | 4 + target/ppc/helper_regs.c | 4 + target/ppc/insn32.decode | 5 + target/ppc/meson.build | 1 + target/ppc/power8-pmu-regs.c.inc | 45 ++- target/ppc/power8-pmu.c | 403 +++++++++++++++++++++++++ target/ppc/power8-pmu.h | 25 ++ target/ppc/spr_tcg.h | 3 + target/ppc/translate.c | 60 ++++ target/ppc/translate/branch-impl.c.inc | 33 ++ 14 files changed, 748 insertions(+), 13 deletions(-) create mode 100644 target/ppc/power8-pmu.c create mode 100644 target/ppc/power8-pmu.h create mode 100644 target/ppc/translate/branch-impl.c.inc -- 2.31.1
