On Wed, Oct 27, 2021 at 8:08 AM Alistair Francis <alistai...@gmail.com>
wrote:
> On Mon, Oct 25, 2021 at 10:55 PM Rahul Pathak <rpat...@ventanamicro.com>
> wrote:
> >
> > Signed-off-by: Rahul Pathak <rpat...@ventanamicro.com>
> > ---
> > target/riscv/cpu.c | 4 +++-
> > target/riscv/cpu.h | 1 +
> > 2 files changed, 4 insertions(+), 1 deletion(-)
> >
> > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > index 788fa0b11c..83c3814a5a 100644
> > --- a/target/riscv/cpu.c
> > +++ b/target/riscv/cpu.c
> > @@ -405,7 +405,9 @@ static void riscv_cpu_realize(DeviceState *dev,
> Error **errp)
> > }
> >
> > if (cpu->cfg.priv_spec) {
> > - if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) {
> > + if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) {
> > + priv_version = PRIV_VERSION_1_12_0;
> > + } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) {
>
> This change, actually allowing the user to enable the spec, should be
> in a separate patch at the end of the series.
>
> The idea is to add the feature, then expose it.
>
Sure, will change in the next version
>
> Alistair
>
>
> > priv_version = PRIV_VERSION_1_11_0;
> > } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) {
> > priv_version = PRIV_VERSION_1_10_0;
> > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> > index a33dc30be8..67c52e6f9e 100644
> > --- a/target/riscv/cpu.h
> > +++ b/target/riscv/cpu.h
> > @@ -79,6 +79,7 @@ enum {
> >
> > #define PRIV_VERSION_1_10_0 0x00011000
> > #define PRIV_VERSION_1_11_0 0x00011100
> > +#define PRIV_VERSION_1_12_0 0x00011200
> >
> > #define VEXT_VERSION_0_07_1 0x00000701
> >
> > --
> > 2.25.1
> >
> >
>
