Re: [PATCH v3 12/21] target/riscv: support for 128-bit U-type instructions

[Richard Henderson]

On 10/19/21 2:48 AM, Frédéric Pétrot wrote:
Adding the 128-bit version of lui and auipc.
Signed-off-by: Frédéric Pétrot <frederic.pet...@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.por...@grenoble-inp.org>
---
  target/riscv/insn_trans/trans_rvi.c.inc | 19 +++++++++++++++++--
  1 file changed, 17 insertions(+), 2 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvi.c.inc 
b/target/riscv/insn_trans/trans_rvi.c.inc
index 92f41f3a86..b5e292a2aa 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -26,14 +26,17 @@ static bool trans_illegal(DisasContext *ctx, arg_empty *a)
  
  static bool trans_c64_illegal(DisasContext *ctx, arg_empty *a)
  {
-     REQUIRE_64BIT(ctx);
-     return trans_illegal(ctx, a);
+    REQUIRE_64_OR_128BIT(ctx);
+    return trans_illegal(ctx, a);
  }
  
  static bool trans_lui(DisasContext *ctx, arg_lui *a)
  {
      if (a->rd != 0) {
          tcg_gen_movi_tl(cpu_gpr[a->rd], a->imm);
+        if (get_xl_max(ctx) == MXL_RV128) {
+            tcg_gen_movi_tl(cpu_gprh[a->rd], -(a->imm < 0));
+        }
      }
      return true;
  }
@@ -41,7 +44,19 @@ static bool trans_lui(DisasContext *ctx, arg_lui *a)
  static bool trans_auipc(DisasContext *ctx, arg_auipc *a)
  {
      if (a->rd != 0) {
+        if (get_xl_max(ctx) == MXL_RV128) {
+            /* TODO : when pc is 128 bits, use all its bits */
+            TCGv pc = tcg_constant_tl(ctx->base.pc_next),
+                 imml = tcg_constant_tl(a->imm),
+                 immh = tcg_constant_tl(-(a->imm < 0)),
+                 zero = tcg_constant_tl(0);
+            tcg_gen_add2_tl(cpu_gpr[a->rd], cpu_gprh[a->rd],
+                            pc, zero,
+                            imml, immh);

A runtime computation of constant + constant is pointless.

I think you should refactor these into a gen_set_gpri, and hide the sign-extension into 
gprh there.


r~