arm queue: big stuff here is my MVE codegen optimisation, and Alex's Apple Silicon hvf support.
-- PMM The following changes since commit 7adb961995a3744f51396502b33ad04a56a317c3: Merge remote-tracking branch 'remotes/dgilbert-gitlab/tags/pull-virtiofs-20210916' into staging (2021-09-19 18:53:29 +0100) are available in the Git repository at: https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210920 for you to fetch changes up to 1dc5a60bfe406bc1122d68cbdefda38d23134b27: target/arm: Optimize MVE 1op-immediate insns (2021-09-20 14:18:01 +0100) ---------------------------------------------------------------- target-arm queue: * Optimize codegen for MVE when predication not active * hvf: Add Apple Silicon support * hw/intc: Set GIC maintenance interrupt level to only 0 or 1 * Fix mishandling of MVE FPSCR.LTPSIZE reset for usermode emulator * elf2dmp: Fix coverity nits ---------------------------------------------------------------- Alexander Graf (7): arm: Move PMC register definitions to internals.h hvf: Add execute to dirty log permission bitmap hvf: Introduce hvf_arch_init() callback hvf: Add Apple Silicon support hvf: arm: Implement PSCI handling arm: Add Hypervisor.framework build target hvf: arm: Add rudimentary PMC support Peter Collingbourne (1): arm/hvf: Add a WFI handler Peter Maydell (18): elf2dmp: Check curl_easy_setopt() return value elf2dmp: Fail cleanly if PDB file specifies zero block_size target/arm: Don't skip M-profile reset entirely in user mode target/arm: Always clear exclusive monitor on reset target/arm: Consolidate ifdef blocks in reset hvf: arm: Implement -cpu host target/arm: Avoid goto_tb if we're trying to exit to the main loop target/arm: Enforce that FPDSCR.LTPSIZE is 4 on inbound migration target/arm: Add TB flag for "MVE insns not predicated" target/arm: Optimize MVE logic ops target/arm: Optimize MVE arithmetic ops target/arm: Optimize MVE VNEG, VABS target/arm: Optimize MVE VDUP target/arm: Optimize MVE VMVN target/arm: Optimize MVE VSHL, VSHR immediate forms target/arm: Optimize MVE VSHLL and VMOVL target/arm: Optimize MVE VSLI and VSRI target/arm: Optimize MVE 1op-immediate insns Shashi Mallela (1): hw/intc: Set GIC maintenance interrupt level to only 0 or 1 meson.build | 8 + include/sysemu/hvf_int.h | 12 +- target/arm/cpu.h | 6 +- target/arm/hvf_arm.h | 18 + target/arm/internals.h | 44 ++ target/arm/kvm_arm.h | 2 - target/arm/translate.h | 2 + accel/hvf/hvf-accel-ops.c | 21 +- contrib/elf2dmp/download.c | 22 +- contrib/elf2dmp/pdb.c | 4 + hw/intc/arm_gicv3_cpuif.c | 5 +- target/arm/cpu.c | 56 +- target/arm/helper.c | 77 ++- target/arm/hvf/hvf.c | 1278 +++++++++++++++++++++++++++++++++++++++++ target/arm/machine.c | 13 + target/arm/translate-m-nocp.c | 8 +- target/arm/translate-mve.c | 310 +++++++--- target/arm/translate-vfp.c | 33 +- target/arm/translate.c | 42 +- target/i386/hvf/hvf.c | 10 + MAINTAINERS | 5 + target/arm/hvf/meson.build | 3 + target/arm/hvf/trace-events | 11 + target/arm/meson.build | 2 + 24 files changed, 1824 insertions(+), 168 deletions(-) create mode 100644 target/arm/hvf_arm.h create mode 100644 target/arm/hvf/hvf.c create mode 100644 target/arm/hvf/meson.build create mode 100644 target/arm/hvf/trace-events
