On Thu, Sep 2, 2021 at 9:18 AM Philippe Mathieu-Daudé <f4...@amsat.org>
wrote:
> Restrict cpu_exec_interrupt() and its callees to sysemu.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4...@amsat.org>
> ---
> target/openrisc/cpu.h | 5 +++--
> target/openrisc/cpu.c | 2 +-
> target/openrisc/interrupt.c | 2 --
> target/openrisc/meson.build | 6 ++++--
> 4 files changed, 8 insertions(+), 7 deletions(-)
>
I'm not 100% sure about the build changes because my meson fu is weak, but
they seem right given the rest.
Reviewed-by: Warner Losh <i...@bsdimp.com>
> diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
> index 82cbaeb4f84..be6df81a810 100644
> --- a/target/openrisc/cpu.h
> +++ b/target/openrisc/cpu.h
> @@ -312,8 +312,6 @@ struct OpenRISCCPU {
>
>
> void cpu_openrisc_list(void);
> -void openrisc_cpu_do_interrupt(CPUState *cpu);
> -bool openrisc_cpu_exec_interrupt(CPUState *cpu, int int_req);
> void openrisc_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
> hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
> int openrisc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int
> reg);
> @@ -331,6 +329,9 @@ int print_insn_or1k(bfd_vma addr, disassemble_info
> *info);
> #ifndef CONFIG_USER_ONLY
> extern const VMStateDescription vmstate_openrisc_cpu;
>
> +void openrisc_cpu_do_interrupt(CPUState *cpu);
> +bool openrisc_cpu_exec_interrupt(CPUState *cpu, int int_req);
> +
> /* hw/openrisc_pic.c */
> void cpu_openrisc_pic_init(OpenRISCCPU *cpu);
>
> diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
> index bd34e429ecb..27cb04152f9 100644
> --- a/target/openrisc/cpu.c
> +++ b/target/openrisc/cpu.c
> @@ -186,10 +186,10 @@ static const struct SysemuCPUOps openrisc_sysemu_ops
> = {
>
> static const struct TCGCPUOps openrisc_tcg_ops = {
> .initialize = openrisc_translate_init,
> - .cpu_exec_interrupt = openrisc_cpu_exec_interrupt,
> .tlb_fill = openrisc_cpu_tlb_fill,
>
> #ifndef CONFIG_USER_ONLY
> + .cpu_exec_interrupt = openrisc_cpu_exec_interrupt,
> .do_interrupt = openrisc_cpu_do_interrupt,
> #endif /* !CONFIG_USER_ONLY */
> };
> diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c
> index 3eab771dcda..19223e3f25b 100644
> --- a/target/openrisc/interrupt.c
> +++ b/target/openrisc/interrupt.c
> @@ -28,7 +28,6 @@
>
> void openrisc_cpu_do_interrupt(CPUState *cs)
> {
> -#ifndef CONFIG_USER_ONLY
> OpenRISCCPU *cpu = OPENRISC_CPU(cs);
> CPUOpenRISCState *env = &cpu->env;
> int exception = cs->exception_index;
> @@ -96,7 +95,6 @@ void openrisc_cpu_do_interrupt(CPUState *cs)
> } else {
> cpu_abort(cs, "Unhandled exception 0x%x\n", exception);
> }
> -#endif
>
> cs->exception_index = -1;
> }
> diff --git a/target/openrisc/meson.build b/target/openrisc/meson.build
> index 9774a583065..e445dec4a00 100644
> --- a/target/openrisc/meson.build
> +++ b/target/openrisc/meson.build
> @@ -9,7 +9,6 @@
> 'exception_helper.c',
> 'fpu_helper.c',
> 'gdbstub.c',
> - 'interrupt.c',
> 'interrupt_helper.c',
> 'mmu.c',
> 'sys_helper.c',
> @@ -17,7 +16,10 @@
> ))
>
> openrisc_softmmu_ss = ss.source_set()
> -openrisc_softmmu_ss.add(files('machine.c'))
> +openrisc_softmmu_ss.add(files(
> + 'interrupt.c',
> + 'machine.c',
> +))
>
> target_arch += {'openrisc': openrisc_ss}
> target_softmmu_arch += {'openrisc': openrisc_softmmu_ss}
> --
> 2.31.1
>
>
