Thanks Peter. On Mon, Oct 24, 2011 at 7:39 PM, Peter Maydell <peter.mayd...@linaro.org>wrote:
> On 24 October 2011 07:46, Carter Cheng <carterch...@gmail.com> wrote: > > I was wondering if someone could help me understand some aspects of the > > current qemu code generation routines. How are floating point and SSE ops > > currently handled? I do not see specific tcg routines for these cases(the > > README seems to indicate that FP and vector ops are not handled using the > > current IL). > > FP instructions are generally turned into code which calls out to > a "helper function" written in C which emulates the floating point > arithmetic -- see target-i386/op_helper.c for the x87 ops and > target-i386/ops_sse.h for the SSE ops. (Some simple arithmetic > vector ops might be done by generating inline code; ARM does this > but I haven't checked target-i386.) IEEE arithmetic emulation > is done in fpu/ but you probably don't need to look at the actual > implementation... > > In the TCG intermediate representation there's no special support > for float/double types -- they're just passed around as i32/i64. > > -- PMM >
