Hi, This second version is considerably different than the first one. All changes were made based on review comments from David and Richard, along with some design changes I decided to make along the way.
Patches were rebased using current David's ppc-for-6.2 tree. Changes from v1: - all patches: * ppc64-linux-user build tested - patches 1-3: * do not expose 'env->spr' to make MMCR0 access control * PMCC was added in hflags to make MMCR0 access control * do not use generalist functions with reg switches - patches 4-8: * helper file was renamed to 'power8_pmu.c' * no longer use icount to count instructions and cycles * cycle counting is now made using time intervals * instruction counting now uses a helper inside translate.c that counts instructions during translation block end * PM_RUN_INST_CMPL (insns completed with run latch) is now implemented accordingly * PM_CMPLU_STALL events were dropped - patches 9-11: * rfebb was implemented from scratch using decode tree - patches 12-16: * cycle overflow now uses 5 independent timers, one for each cycle capable counter * instruction overflow is now triggered via the translation.c helper * new patch (16): add capability to enable/disable cycle counter overflow when the PMU is running - documentation patch was dropped for now. I will re-send it when this work is more ironed out. v1 link: https://lists.gnu.org/archive/html/qemu-devel/2021-08/msg01477.html Daniel Henrique Barboza (13): target/ppc: add user write access control for PMU SPRs target/ppc: PMU basic cycle count for pseries TCG target/ppc/power8_pmu.c: enable PMC1-PMC4 events target/ppc: PMU: add instruction counting target/ppc/power8_pmu.c: add PM_RUN_INST_CMPL (0xFA) event target/ppc/power8_pmu.c: add PMC14/PMC56 counter freeze bits PPC64/TCG: Implement 'rfebb' instruction target/ppc/excp_helper.c: EBB handling adjustments target/ppc/power8_pmu.c: enable PMC1 counter negative overflow target/ppc/power8_pmu.c: cycles overflow with all PMCs target/ppc: PMU: insns counter negative overflow support target/ppc/translate: PMU: handle setting of PMCs while running target/ppc/power8_pmu.c: handle overflow bits when PMU is running Gustavo Romero (3): target/ppc: add user read functions for MMCR0 and MMCR2 target/ppc: add exclusive user write function for MMCR0 target/ppc: PMU Event-Based exception support hw/ppc/spapr_cpu_core.c | 6 + target/ppc/cpu.h | 55 ++- target/ppc/cpu_init.c | 36 +- target/ppc/excp_helper.c | 85 +++++ target/ppc/helper.h | 4 + target/ppc/helper_regs.c | 3 + target/ppc/insn32.decode | 5 + target/ppc/meson.build | 1 + target/ppc/power8_pmu.c | 467 +++++++++++++++++++++++++ target/ppc/power8_pmu.h | 25 ++ target/ppc/spr_tcg.h | 7 + target/ppc/translate.c | 218 ++++++++++++ target/ppc/translate/branch-impl.c.inc | 32 ++ 13 files changed, 925 insertions(+), 19 deletions(-) create mode 100644 target/ppc/power8_pmu.c create mode 100644 target/ppc/power8_pmu.h create mode 100644 target/ppc/translate/branch-impl.c.inc -- 2.31.1
