Hi,
This series adds the minimum set of models (XIVE2, PHB5) to boot a
baremetal POWER10 machine using the OpenPOWER firmware images.
The major change is the support for the interrupt controller of the
POWER10 processor. XIVE2 is very much like XIVE but the register
interface, the different MMIO regions, the XIVE internal descriptors
have gone through a major cleanup. It was easier to duplicate the
models then to try to adapt the current models. XIVE2 adds some new
set of features. Not all are modeled here but we add the
"Address-based trigger" mode which is activated by default on the
PHB5. When using ABT, the PHB5 offloads all interrupt management on
the IC, this to improve latency.
Thanks,
C.
Cédric Le Goater (26):
ppc: Add a POWER10 DD2 CPU
ppc/pnv: Change the POWER10 machine to support DD2 only
ppc/pnv: powerpc_excp: Do not discard HDECR exception when entering
power-saving mode
ppc/pnv: Use a simple incrementing index for the chip-id
ppc/pnv: Distribute RAM among the chips
ppc/pnv: add a chip topology index for POWER10
ppc/xive: Export PQ get/set routines
ppc/xive: Export xive_presenter_notify()
ppc/xive2: Introduce a XIVE2 core framework
ppc/xive2: Introduce a presenter matching routine
ppc/pnv: Add a XIVE2 controller to the POWER10 chip.
ppc/pnv: Add a OCC model for POWER10
ppc/pnv: Add POWER10 quads
ppc/pnv: Add model for POWER10 PHB5 PCIe Host bridge
ppc/pnv: Add a HOMER model to POWER10
ppc/psi: Add support for StoreEOI and 64k ESB pages (POWER10)
ppc/xive2: Add support for notification injection on ESB pages
ppc/xive: Add support for PQ state bits offload
ppc/pnv: Add support for PQ offload on PHB5
ppc/pnv: Add support for PHB5 "Address-based trigger" mode
pnv/xive2: Introduce new capability bits
ppc/pnv: add XIVE Gen2 TIMA support
pnv/xive2: Add support XIVE2 P9-compat mode (or Gen1)
xive2: Add a get_config() handler for the router configuration
pnv/xive2: Add support for automatic save&restore
pnv/xive2: Add support for 8bits thread id
hw/intc/pnv_xive2_regs.h | 442 ++++++
include/hw/pci-host/pnv_phb4.h | 11 +
include/hw/pci-host/pnv_phb4_regs.h | 3 +
include/hw/ppc/pnv.h | 74 +-
include/hw/ppc/pnv_homer.h | 3 +
include/hw/ppc/pnv_occ.h | 2 +
include/hw/ppc/pnv_xive.h | 75 +
include/hw/ppc/pnv_xscom.h | 15 +
include/hw/ppc/xive.h | 18 +-
include/hw/ppc/xive2.h | 115 ++
include/hw/ppc/xive2_regs.h | 210 +++
target/ppc/cpu-models.h | 1 +
hw/intc/pnv_xive.c | 37 +-
hw/intc/pnv_xive2.c | 2127 +++++++++++++++++++++++++++
hw/intc/spapr_xive.c | 25 +
hw/intc/spapr_xive_kvm.c | 8 +-
hw/intc/xive.c | 91 +-
hw/intc/xive2.c | 1028 +++++++++++++
hw/pci-host/pnv_phb4.c | 87 +-
hw/pci-host/pnv_phb4_pec.c | 44 +
hw/ppc/pnv.c | 294 +++-
hw/ppc/pnv_core.c | 2 +-
hw/ppc/pnv_homer.c | 64 +
hw/ppc/pnv_occ.c | 16 +
hw/ppc/pnv_psi.c | 38 +-
hw/ppc/pnv_xscom.c | 2 +
target/ppc/cpu-models.c | 4 +-
target/ppc/cpu_init.c | 3 +
target/ppc/excp_helper.c | 6 -
hw/intc/meson.build | 4 +-
hw/pci-host/trace-events | 2 +
31 files changed, 4760 insertions(+), 91 deletions(-)
create mode 100644 hw/intc/pnv_xive2_regs.h
create mode 100644 include/hw/ppc/xive2.h
create mode 100644 include/hw/ppc/xive2_regs.h
create mode 100644 hw/intc/pnv_xive2.c
create mode 100644 hw/intc/xive2.c
--
2.31.1
