This patchset fixes a handful of minor M-profile bugs:
* The low 2 bits of SP should not be writeable (they are always 0)
* Missing 'return' statements for some "tail chain to another
exception after detecting an error during exception return" cases
* Alignment faults were being incorrectly reported to the guest
as MMU faults
* ISCR.ISRPENDING wasn't being set if there was a pending
but non-enabled interrupt
* ISCR.VECTPENDING is 9 bits, not 8
* ISCR.VECTPENDING was missing the new-for-v8.1M behaviour where
it hides the identity of a pending Secure exception from a
NonSecure read of the register
Nothing here is very critical, but they might as well go into
6.1 because they are bugfixes.
thanks
-- PMM
Peter Maydell (6):
target/arm: Enforce that M-profile SP low 2 bits are always zero
target/arm: Add missing 'return's after calling v7m_exception_taken()
target/arm: Report M-profile alignment faults correctly to the guest
hw/intc/armv7m_nvic: ISCR.ISRPENDING is set for non-enabled pending
interrupts
hw/intc/armv7m_nvic: Correct size of ICSR.VECTPENDING
hw/intc/armv7m_nvic: for v8.1M VECTPENDING hides S exceptions from NS
hw/intc/armv7m_nvic.c | 40 ++++++++++++++++++++++++++++------------
target/arm/gdbstub.c | 4 ++++
target/arm/m_helper.c | 24 ++++++++++++++++++------
target/arm/translate.c | 3 +++
4 files changed, 53 insertions(+), 18 deletions(-)
--
2.20.1
