Commit 043715d1e0f ("target/mips: Update ITU to utilize SAARI
and SAAR CP0 registers") declared itc_reconfigure() in public
namespace, while it is restricted to system emulation.
Similarly commit 5679479b9a1 ("target/mips: Move CP0 helpers
to sysemu/cp0.c") restricted cpu_mips_soft_irq() definition to
system emulation, but forgot to restrict its declaration.
To avoid polluting user-mode emulation with these declarations,
restrict them to sysemu. Also restrict the sysemu ITU/ITC/IRQ
fields from CPUMIPSState.
Signed-off-by: Philippe Mathieu-Daudé <f4...@amsat.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-Id: <20210617174323.2900831-6-f4...@amsat.org>
---
target/mips/cpu.h | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 075c24abdad..1dfe69c6c0c 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -1152,13 +1152,13 @@ struct CPUMIPSState {
CPUMIPSMVPContext *mvp;
#if !defined(CONFIG_USER_ONLY)
CPUMIPSTLBContext *tlb;
+ void *irq[8];
+ struct MIPSITUState *itu;
+ MemoryRegion *itc_tag; /* ITC Configuration Tags */
#endif
const mips_def_t *cpu_model;
- void *irq[8];
QEMUTimer *timer; /* Internal timer */
- struct MIPSITUState *itu;
- MemoryRegion *itc_tag; /* ITC Configuration Tags */
target_ulong exception_base; /* ExceptionBase input to the core */
uint64_t cp0_count_ns; /* CP0_Count clock period (in nanoseconds) */
};
@@ -1316,12 +1316,16 @@ uint64_t cpu_mips_phys_to_kseg1(void *opaque, uint64_t
addr);
bool mips_um_ksegs_enabled(void);
void mips_um_ksegs_enable(void);
+#if !defined(CONFIG_USER_ONLY)
+
/* mips_int.c */
void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level);
/* mips_itu.c */
void itc_reconfigure(struct MIPSITUState *tag);
+#endif /* !CONFIG_USER_ONLY */
+
/* helper.c */
target_ulong exception_resume_pc(CPUMIPSState *env);
--
2.31.1
