The following changes since commit d0ac9a61474cf594d19082bc8976247e984ea9a3:
Merge remote-tracking branch
'remotes/thuth-gitlab/tags/pull-request-2021-06-21' into staging (2021-06-24
09:31:26 +0100)
are available in the Git repository at:
g...@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210624-2
for you to fetch changes up to 3ef6434409c575e11faf537ce50ca05426c78940:
hw/riscv: OpenTitan: Connect the mtime and mtimecmp timer (2021-06-24
05:00:13 -0700)
----------------------------------------------------------------
Third RISC-V PR for 6.1 release
- Fix MISA in the DisasContext
- Fix GDB CSR XML generation
- QOMify the SiFive UART
- Add support for the OpenTitan timer
----------------------------------------------------------------
Alistair Francis (4):
target/riscv: Use target_ulong for the DisasContext misa
hw/char/ibex_uart: Make the register layout private
hw/timer: Initial commit of Ibex Timer
hw/riscv: OpenTitan: Connect the mtime and mtimecmp timer
Bin Meng (1):
target/riscv: gdbstub: Fix dynamic CSR XML generation
Lukas Jünger (2):
hw/char: Consistent function names for sifive_uart
hw/char: QOMify sifive_uart
include/hw/char/ibex_uart.h | 37 -----
include/hw/char/sifive_uart.h | 11 +-
include/hw/riscv/opentitan.h | 5 +-
include/hw/timer/ibex_timer.h | 52 +++++++
hw/char/ibex_uart.c | 37 +++++
hw/char/sifive_uart.c | 152 +++++++++++++++++----
hw/riscv/opentitan.c | 14 +-
hw/timer/ibex_timer.c | 305 ++++++++++++++++++++++++++++++++++++++++++
target/riscv/gdbstub.c | 2 +-
target/riscv/translate.c | 2 +-
MAINTAINERS | 6 +-
hw/timer/meson.build | 1 +
12 files changed, 543 insertions(+), 81 deletions(-)
create mode 100644 include/hw/timer/ibex_timer.h
create mode 100644 hw/timer/ibex_timer.c
