On Mon, 21 Jun 2021 at 20:50, Richard Henderson <richard.hender...@linaro.org> wrote: > > On 6/21/21 12:40 PM, Peter Maydell wrote: > > On Mon, 21 Jun 2021 at 19:12, Richard Henderson > > <richard.hender...@linaro.org> wrote: > >> > >> On 6/21/21 7:01 AM, Peter Maydell wrote: > >>> Side note: it's rather confusing that tcg_out_rev32() doesn't > >>> emit a REV32 insn (it emits REV with sf==0). > >> > >> Which is REV with SF=0 also has OPC=10, which is REV32. > > > > No, REV32 has SF=1. The two operations are different: > > > > REV <Wd>, <Wn> -- swaps byte order of the bottom 32 bits > > (zeroes the top half of Xd, as usual for Wn ops) > > REV32 <Xd>, <Xn> -- swaps byte order of bottom 32 bits and > > also swaps byte order of top 32 bits > > (ie it is a 64-bit to 64-bit operation > > which does does two bswap32()s) > > Ignore the assembler mnemonic and look at the opcode:
...but the point is that tcg_out_rev32() is not doing the thing that the assembler insn REV32 does, so ignoring the mnemonic is missing the point. > REV Wd,Wn = SF=0, OPC=10 > REV32 Xd,Xn = SF=1, OPC=10 > REV Xd,Xn = SF=1, OPC=11 > > REV(Wd,Wd) = (uint32_t)REV32(Xd,Xd) > i.e. the usual interpretation of sf=0. You could look at it that way, but that's not the way the insn mnemonics have been defined... -- PMM
