This attempts to fix the x86 denormal-exception flag, which is the inverse of the existing float_flag_input_denormal flag. I have not created a new test case for this yet, fwiw.
While auditing all uses of float_flag_*_denormal, I found some errors in target/rx and target/mips. This is based on my current softfloat conversion for floatx80: Based-on: <20210525150706.294968-1-richard.hender...@linaro.org> The complete tree may be found at https://gitlab.com/rth7680/qemu/-/commits/fpu-test-5 r~ Richard Henderson (11): softfloat: Rename float_flag_input_denormal to float_flag_iflush_denormal softfloat: Rename float_flag_output_denormal to float_flag_oflush_denormal softfloat: Introduce float_flag_inorm_denormal softfloat: Introduce float_flag_result_denormal target/i386: Use float_flag_inorm_denormal target/rx: Handle the FPSW.DN bit in helper_set_fpsw target/rx: Use FloatRoundMode in helper_set_fpsw target/rx: Fix setting of FPSW.CE target/mips: Drop inline markers from msa_helper.c target/mips: Do not check MSACSR_FS_MASK in update_msacsr target/mips: Drop denormal operand to update_msacsr include/fpu/softfloat-types.h | 18 +- fpu/softfloat.c | 88 ++++------ target/arm/sve_helper.c | 6 +- target/arm/vfp_helper.c | 12 +- target/i386/tcg/fpu_helper.c | 18 +- target/mips/tcg/msa_helper.c | 298 +++++++++++++++------------------- target/rx/op_helper.c | 19 ++- target/tricore/fpu_helper.c | 6 +- fpu/softfloat-parts.c.inc | 13 +- 9 files changed, 212 insertions(+), 266 deletions(-) -- 2.25.1
