> We can use it directly if only one macro VS_MODE_INTERRUPTS. I wrote it like this to be more coherent with what was already there which also makes it more readable. Furthermore, the compiler will just probably optimize the variable away, right?
> I didn't find that the RISCV_EXCP_VS_ECALL should be read-only 0 from the > specification. You are right. I had doubts about this also. The table that defines it in the spec is missing this bit. I raised an issue on the spec repo (https://github.com/riscv/riscv-isa-manual/issues/649). But in my opinion, it wouldn't really make sense to allow this exception to be delegated. What do you think? Is there any use case for this to be allowed? Maybe we'll need a clarification from the spec to reach a final decision. > However, as hedeleg is WARL, you had better reserve the other fields like > medeleg: > > env->medeleg = (env->medeleg & ~delegable_excps) | (val & delegable_excps); Isn't the patch's implementation of hedeleg/hideleg providing a WARL behavior already? I don't think we need this preservation behavior since in the case of hideleg/hedeleg there can only be 0-wired bits. I believe this won't change. For hedeleg the spec states that "Each bit of hedeleg shall be either writable or hardwired to zero". For hideleg: "Among bits 15:0 of hideleg, only bits 10, 6, and 2 (corresponding to the standard VS-level interrupts) shall be writable, and the others shall be hardwired to zero." > I really don't understand why medeleg codes this way. Is there anyone can > give a better explanation? I don't know if I fully understood your question, but I don't get why you would need to preserve non-delegable bits in medeleg in this way, even to keep WARL behavior. Again, the specification only allows medeleg bits to be hardwired to zero: "An implementation shall not hardwire any bits of medeleg to one, i.e., any synchronous trap that can be delegated must support not being delegated.", so a bitwise-and should suffice. José
