Re: [PATCH] target/riscv: hardwire bits in hideleg and hedeleg

[LIU Zhiwei]

On 5/22/21 11:59 PM, Jose Martins wrote:
The specification mandates for certain bits to be hardwired in the
hypervisor delegation registers. This was not being enforced.
Signed-off-by: Jose Martins <josemartin...@gmail.com>
---
  target/riscv/csr.c | 13 +++++++++++--
  1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index d2585395bf..9b74a00cc9 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -394,6 +394,7 @@ static int read_timeh(CPURISCVState *env, int csrno, 
target_ulong *val)
  
  static const target_ulong delegable_ints = S_MODE_INTERRUPTS |
                                             VS_MODE_INTERRUPTS;
+static const target_ulong vs_delegable_ints = VS_MODE_INTERRUPTS;
We can use it directly if only one macro VS_MODE_INTERRUPTS.
  static const target_ulong all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS |
                                       VS_MODE_INTERRUPTS;
  static const target_ulong delegable_excps =
@@ -416,6 +417,14 @@ static const target_ulong delegable_excps =
      (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) |
      (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) |
      (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT));
+static const target_ulong vs_delegable_excps = delegable_excps &
+    ~((1ULL << (RISCV_EXCP_S_ECALL)) |
+    (1ULL << (RISCV_EXCP_VS_ECALL)) |
I didn't find that the RISCV_EXCP_VS_ECALL should be read-only 0 from 
the specification.
+    (1ULL << (RISCV_EXCP_M_ECALL)) |
+    (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) |
+    (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) |
+    (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) |
+    (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT)));
  static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
      SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
      SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD;
@@ -963,7 +972,7 @@ static int read_hedeleg(CPURISCVState *env, int csrno, 
target_ulong *val)
  
  static int write_hedeleg(CPURISCVState *env, int csrno, target_ulong val)
  {
-    env->hedeleg = val;
+    env->hedeleg = val & vs_delegable_excps;

I think it's OK here.

However, as hedeleg is WARL, you had better reserve the other fields 
like medeleg:

        env->medeleg = (env->medeleg & ~delegable_excps) | (val & 
delegable_excps);

I really don't understand why medeleg codes this way. Is there anyone 
can give a better explanation?

      return 0;
  }
  
@@ -975,7 +984,7 @@ static int read_hideleg(CPURISCVState *env, int csrno, target_ulong *val)
  
  static int write_hideleg(CPURISCVState *env, int csrno, target_ulong val)
  {
-    env->hideleg = val;
+    env->hideleg = val & vs_delegable_ints;
      return 0;
  }
  

The similar comments for hedeleg.

Zhiwei