On 5/21/21 6:55 AM, Alistair Francis wrote:
On Thu, May 20, 2021 at 11:55 PM Peter Maydell <peter.mayd...@linaro.org> wrote:
On Tue, 11 May 2021 at 11:22, Alistair Francis <alistair.fran...@wdc.com> wrote:
Signed-off-by: Alistair Francis <alistair.fran...@wdc.com>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-id:
fcc125d96da941b56c817c9dd6068dc36478fc53.1619234854.git.alistair.fran...@wdc.com
---
target/riscv/cpu_bits.h | 10 ----------
target/riscv/csr.c | 12 ++++++++++--
target/riscv/translate.c | 19 +++++++++++++++++--
3 files changed, 27 insertions(+), 14 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 26eccc5eb1..a596f80f20 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -78,6 +78,17 @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext)
return ctx->misa & ext;
}
+#ifdef TARGET_RISCV32
+# define is_32bit(ctx) true
+#elif defined(CONFIG_USER_ONLY)
+# define is_32bit(ctx) false
+#else
+static inline bool is_32bit(DisasContext *ctx)
+{
+ return (ctx->misa & RV32) == RV32;
+}
+#endif
Hi; Coverity points out (CID 1453107) that this is_32bit() function
can never return true for at least some build configs, because RV32
is defined as ((target_ulong)1 << (TARGET_LONG_BITS - 2))
but ctx->misa is a uint32_t field, which (if TARGET_LONG_BITS is
64) is not big enough for the RV32 bit.
This seems like a false positive as RV32 is defined as:
((target_ulong)1 << (TARGET_LONG_BITS - 2))
while ctx->misa is a target_ulong.
Although the misa in RISCVCPUState is target_ulong, the misa in
DisasContext is uint32_t.
I think we should fix up the misa in DisasContext.
Zhiwei
So it should always be able to return true.
Alistair
Bug, or false positive ?
thanks
-- PMM
