Hello Francis, Yes thank you. I added code to setup a basic PMP and it works now. Thank you and best regards,
Teodori Serge On Sun, 18 Apr 2021, 05:55 Alistair Francis, <1923...@bugs.launchpad.net> wrote: > We fixed a bug to make QEMU act more like hardware, which now means that > PMP must be configured in M-mode. > > -- > You received this bug notification because you are subscribed to the bug > report. > https://bugs.launchpad.net/bugs/1923197 > > Title: > RISC-V priviledged instruction error > > To manage notifications about this bug go to: > https://bugs.launchpad.net/qemu/+bug/1923197/+subscriptions > -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1923197 Title: RISC-V priviledged instruction error Status in QEMU: Invalid Bug description: Hello when performing an MRET with MPP set to something else than 0b11 in MSTATUS, 'Invalid Instruction' exception will be triggered. The problem appeared in code after version 5.2.0. Use following code to test. # setup interrupt handling for monitor mode la t0, entry_loop la t1, entry_trap li t2, 0x888 li t3, 0x1880 csrw mepc, t0 csrw mtvec, t1 csrs mie, t2 csrs mstatus, t3 # if supervisor mode not supported, then loop forever csrr t0, misa li t1, 0x40000 and t2, t1, t0 beqz t2, 1f # setup interrupt i& exception delegation for supervisor mode li t0, 0xc0000000 # 3 GiB (entry address of supervisor) li t1, 0x1000 li t2, 0x300 li t3, 0x222 csrw mepc, t0 csrc mstatus, t1 csrs medeleg, t2 csrs mideleg, t3 # pass mhartid as first parameter to supervisor csrr a0, mhartid 1: mret To manage notifications about this bug go to: https://bugs.launchpad.net/qemu/+bug/1923197/+subscriptions
