Re: [PATCH 1/3] target/arm: Add support for FEAT_SSBS, Speculative Store Bypass Safe

[Rebecca Cran]

On 2/15/21 5:19 PM, Richard Henderson wrote:
On 2/15/21 1:58 PM, Rebecca Cran wrote:
@@ -960,6 +960,12 @@ static void cpsr_write_from_spsr_elx(CPUARMState *env,
          val |= CPSR_DIT;
      }
  
+    /* Move SSBS to the correct location for CPSR */
+    if (val & PSTATE_SSBS) {
+        val &= ~PSTATE_SSBS;
+        val |= CPSR_SSBS;
+    }

Incorrect.  SPSR_ELx leaves this at the same position as CPSR: bit 23.

Okay, I see where I'm going wrong now - SPSR_ELx has different formats 
for exceptions taken from aarch32 and aarch64 states, which I hadn't 
fully understood. I'll fix it.

--
Rebecca Cran