On 2/15/21 1:58 PM, Rebecca Cran wrote:
> @@ -960,6 +960,12 @@ static void cpsr_write_from_spsr_elx(CPUARMState *env,
> val |= CPSR_DIT;
> }
>
> + /* Move SSBS to the correct location for CPSR */
> + if (val & PSTATE_SSBS) {
> + val &= ~PSTATE_SSBS;
> + val |= CPSR_SSBS;
> + }
Incorrect. SPSR_ELx leaves this at the same position as CPSR: bit 23.
> }
> +
> + if (cpu_isar_feature(aa32_ssbs, env_archcpu(env))) {
> + if (env->cp15.sctlr_el[new_el] & SCTLR_DSSBS_32) {
> + env->uncached_cpsr |= CPSR_SSBS;
> + } else {
> + env->uncached_cpsr &= ~CPSR_SSBS;
> + }
> + }
Hoist this so that it can be shared with the HYP branch (hsctlr is mapped to
sctlr_el[2] and HYP maps to el=2).
> @@ -9809,6 +9846,13 @@ static uint32_t cpsr_read_for_spsr_elx(CPUARMState
> *env)
> ret &= ~CPSR_DIT;
> ret |= PSTATE_DIT;
> }
> +
> + /* Move SSBS to the correct location for SPSR_ELx */
> + if (ret & CPSR_SSBS) {
> + ret &= ~CPSR_SSBS;
> + ret |= PSTATE_SSBS;
> + }
Incorrect, like in cpsr_write_from_spsr_elx.
> diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
> index 1c4b8d02f3b8..2372d55ea18b 100644
> --- a/target/arm/translate-a64.c
> +++ b/target/arm/translate-a64.c
> @@ -1712,6 +1712,18 @@ static void handle_msr_i(DisasContext *s, uint32_t
> insn,
> /* There's no need to rebuild hflags because DIT is a nop */
> break;
>
> + case 0x19: /* SSBS */
> + if (!dc_isar_feature(aa64_ssbs, s)) {
> + goto do_unallocated;
> + }
> + if (crm & 1) {
> + set_pstate_bits(PSTATE_SSBS);
> + } else {
> + clear_pstate_bits(PSTATE_SSBS);
> + }
> + /* Don't need to rebuild hflags since SSBS is a nop */
> + break;
Put this above DIT (0x1a) to keep the numbers in order.
r~
