On Fri, Jan 22, 2021 at 9:36 PM Bin Meng <bmeng...@gmail.com> wrote: > > On Tue, Jan 19, 2021 at 9:40 PM Bin Meng <bmeng...@gmail.com> wrote: > > > > From: Bin Meng <bin.m...@windriver.com> > > > > This v8 series is based on the following 2 versions: > > > > - v5 series sent from Bin > > http://patchwork.ozlabs.org/project/qemu-devel/list/?series=223919 > > - v7 series sent from Philippe > > http://patchwork.ozlabs.org/project/qemu-devel/list/?series=224612 > > > > This series fixes a bunch of bugs in current implementation of the imx > > spi controller, including the following issues: > > > > - remove imx_spi_update_irq() in imx_spi_reset() > > - chip select signal was not lower down when spi controller is disabled > > - round up the tx burst length to be multiple of 8 > > - transfer incorrect data when the burst length is larger than 32 bit > > - spi controller tx and rx fifo endianness is incorrect > > - remove pointless variable (s->burst_length) initialization (Philippe) > > - rework imx_spi_reset() to keep CONREG register value (Philippe) > > - rework imx_spi_read() to handle block disabled (Philippe) > > - rework imx_spi_write() to handle block disabled (Philippe) > > > > Tested with upstream U-Boot v2020.10 (polling mode) and VxWorks 7 > > (interrupt mode). > > > > Changes in v8: > > - keep the controller disable logic in the ECSPI_CONREG case > > in imx_spi_write() > > Ping?
Could we get this applied soon if no more comments? Regards, Bin
