On Tue, 19 Jan 2021 at 13:40, Bin Meng <bmeng...@gmail.com> wrote:
>
> From: Bin Meng <bin.m...@windriver.com>
>
> The endianness of data exchange between tx and rx fifo is incorrect.
> Earlier bytes are supposed to show up on MSB and later bytes on LSB,
> ie: in big endian. The manual does not explicitly say this, but the
> U-Boot and Linux driver codes have a swap on the data transferred
> to tx fifo and from rx fifo.
>
> With this change, U-Boot read from / write to SPI flash tests pass.
>
> => sf test 1ff000 1000
> SPI flash test:
> 0 erase: 0 ticks, 4096000 KiB/s 32768.000 Mbps
> 1 check: 3 ticks, 1333 KiB/s 10.664 Mbps
> 2 write: 235 ticks, 17 KiB/s 0.136 Mbps
> 3 read: 2 ticks, 2000 KiB/s 16.000 Mbps
> Test passed
> 0 erase: 0 ticks, 4096000 KiB/s 32768.000 Mbps
> 1 check: 3 ticks, 1333 KiB/s 10.664 Mbps
> 2 write: 235 ticks, 17 KiB/s 0.136 Mbps
> 3 read: 2 ticks, 2000 KiB/s 16.000 Mbps
>
> Fixes: c906a3a01582 ("i.MX: Add the Freescale SPI Controller")
> Signed-off-by: Bin Meng <bin.m...@windriver.com>
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
thanks
-- PMM
