On 1/21/21 6:45 PM, Rebecca Cran wrote:
> cpsr has been treated as being the same as spsr, but it isn't.
> Since PSTATE_SS isn't in cpsr, remove it and move it into env->pstate.
>
> Signed-off-by: Rebecca Cran <rebe...@nuviainc.com>
> ---
> target/arm/helper-a64.c | 4 +---
> target/arm/helper.c | 4 ++--
> target/arm/op_helper.c | 9 +--------
> 3 files changed, 4 insertions(+), 13 deletions(-)
>
> diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
> index c426c23d2c4e..0d2ac7bb7ee3 100644
> --- a/target/arm/helper-a64.c
> +++ b/target/arm/helper-a64.c
> @@ -1000,9 +1000,7 @@ void HELPER(exception_return)(CPUARMState *env,
> uint64_t new_pc)
> */
> mask = aarch32_cpsr_valid_mask(env->features,
> &env_archcpu(env)->isar);
> cpsr_write(env, spsr, mask, CPSRWriteRaw);
> - if (!arm_singlestep_active(env)) {
> - env->uncached_cpsr &= ~PSTATE_SS;
> - }
> + env->pstate &= ~PSTATE_SS;
Why are you removing the singlestep check?
> aarch64_sync_64_to_32(env);
>
> if (spsr & CPSR_T) {
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index d2ead3fcbdbd..01b50316046b 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -9402,8 +9402,8 @@ static void take_aarch32_exception(CPUARMState *env,
> int new_mode,
> * For exceptions taken to AArch32 we must clear the SS bit in both
> * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it
> now.
> */
> - env->uncached_cpsr &= ~PSTATE_SS;
> - env->spsr = cpsr_read(env);
> + env->pstate &= ~PSTATE_SS;
> + env->spsr &= ~PSTATE_SS;
This loses the saving of cpsr into spsr.
r~
