Hi Peter,
On 1/21/21 8:06 PM, Peter Maydell wrote:
> Convert the SSYS code in the Stellaris boards (which encapsulates the
> system registers) to a proper QOM device. This will provide us with
> somewhere to put the output Clock whose frequency depends on the
> setting of the PLL configuration registers.
>
> This is a migration compatibility break for lm3s811evb, lm3s6965evb.
>
> We use 3-phase reset here because the Clock will need to propagate
> its value in the hold phase.
>
> For the moment we reset the device during the board creation so that
> the system_clock_scale global gets set; this will be removed in a
> subsequent commit.
>
> Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
> ---
> hw/arm/stellaris.c | 132 ++++++++++++++++++++++++++++++++++++---------
> 1 file changed, 107 insertions(+), 25 deletions(-)
>
> diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
> index 652823195b1..0194ede2fe0 100644
> --- a/hw/arm/stellaris.c
> +++ b/hw/arm/stellaris.c
> @@ -357,7 +357,12 @@ static void stellaris_gptm_realize(DeviceState *dev,
> Error **errp)
>
> /* System controller. */
>
> -typedef struct {
> +#define TYPE_STELLARIS_SYS "stellaris-sys"
> +OBJECT_DECLARE_SIMPLE_TYPE(ssys_state, STELLARIS_SYS)
> +
> +struct ssys_state {
> + SysBusDevice parent_obj;
> +
> MemoryRegion iomem;
> uint32_t pborctl;
> uint32_t ldopctl;
> @@ -371,11 +376,18 @@ typedef struct {
> uint32_t dcgc[3];
> uint32_t clkvclr;
> uint32_t ldoarst;
> + qemu_irq irq;
> + /* Properties (all read-only registers) */
> uint32_t user0;
> uint32_t user1;
> - qemu_irq irq;
> - stellaris_board_info *board;
> -} ssys_state;
> + uint32_t did0;
> + uint32_t did1;
> + uint32_t dc0;
> + uint32_t dc1;
> + uint32_t dc2;
> + uint32_t dc3;
> + uint32_t dc4;
Shouldn't these be class properties?
> +};
