Patchew URL: https://patchew.org/QEMU/20210112093950.17530-1-frank.ch...@sifive.com/
Hi, This series seems to have some coding style problems. See output below for more information: Type: series Message-id: 20210112093950.17530-1-frank.ch...@sifive.com Subject: [PATCH v6 00/72] support vector extension v1.0 === TEST SCRIPT BEGIN === #!/bin/bash git rev-parse base > /dev/null || exit 0 git config --local diff.renamelimit 0 git config --local diff.renames True git config --local diff.algorithm histogram ./scripts/checkpatch.pl --mailback base.. === TEST SCRIPT END === Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384 From https://github.com/patchew-project/qemu - [tag update] patchew/20210111115017.156802-1-stefa...@redhat.com -> patchew/20210111115017.156802-1-stefa...@redhat.com - [tag update] patchew/20210111152020.1422021-1-phi...@redhat.com -> patchew/20210111152020.1422021-1-phi...@redhat.com * [new tag] patchew/20210112093950.17530-1-frank.ch...@sifive.com -> patchew/20210112093950.17530-1-frank.ch...@sifive.com - [tag update] patchew/cover.1610384501.git.mreza...@redhat.com -> patchew/cover.1610384501.git.mreza...@redhat.com Switched to a new branch 'test' e79af24 target/riscv: set mstatus.SD bit when writing fp CSRs bac292a target/riscv: rvv-1.0: floating-point reciprocal estimate instruction 9a31731 target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction e2e0371 target/riscv: gdb: support vector registers for rv64 & rv32 eb47c13 target/riscv: gdb: modify gdb csr xml file to align with csr register map 3f07b9a target/riscv: rvv-1.0: set mstatus.SD bit when writing vector CSRs 81cdec9 target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid e9df65e target/riscv: rvv-1.0: implement vstart CSR d5b6972 target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits 518bc3c target/riscv: rvv-1.0: narrowing floating-point/integer type-convert 523b3cc target/riscv: add "set round to odd" rounding mode helper function 5982271 target/riscv: rvv-1.0: widening floating-point/integer type-convert c056e25 target/riscv: rvv-1.0: floating-point/integer type-convert instructions 76ffa24 target/riscv: introduce floating-point rounding mode enum 511c21a target/riscv: rvv-1.0: floating-point min/max instructions 3179608 target/riscv: rvv-1.0: remove integer extract instruction b0e7ad9 target/riscv: rvv-1.0: remove vmford.vv and vmford.vf 241debb target/riscv: rvv-1.0: remove widening saturating scaled multiply-add bd98d71 target/riscv: rvv-1.0: single-width scaling shift instructions bddb386 target/riscv: rvv-1.0: widening floating-point reduction instructions 6a43922 target/riscv: rvv-1.0: single-width floating-point reduction a54617f target/riscv: rvv-1.0: narrowing fixed-point clip instructions 37b1bba target/riscv: rvv-1.0: floating-point slide instructions ba9b3d7 target/riscv: rvv-1.0: slide instructions 0d96fb8 target/riscv: rvv-1.0: mask-register logical instructions c0a16ee target/riscv: rvv-1.0: floating-point compare instructions 11c0e36 target/riscv: rvv-1.0: integer comparison instructions 64635ad target/riscv: rvv-1.0: single-width saturating add and subtract instructions 5f4c001 target/riscv: rvv-1.0: widening integer multiply-add instructions 9e00723 target/riscv: rvv-1.0: narrowing integer right shift instructions 591bb6e target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow 9587159 target/riscv: rvv-1.0: single-width bit shift instructions 4982bd6 target/riscv: rvv-1.0: single-width averaging add and subtract instructions f9c9b41 target/riscv: rvv-1.0: integer extension instructions 78f16c1 target/riscv: rvv-1.0: whole register move instructions 4fe5bbf target/riscv: rvv-1.0: floating-point scalar move instructions 08e8122 target/riscv: rvv-1.0: floating-point move instruction af81a16 target/riscv: rvv-1.0: integer scalar move instructions f692e27 target/riscv: rvv-1.0: register gather instructions 0931fb7 target/riscv: rvv-1.0: allow load element with sign-extended 9bb22ce target/riscv: rvv-1.0: element index instruction 74692f6 target/riscv: rvv-1.0: iota instruction 7fb6361 target/riscv: rvv-1.0: set-X-first mask bit instructions 8466af8 target/riscv: rvv-1.0: find-first-set mask bit instruction 5e71b3f target/riscv: rvv-1.0: mask population count instruction 7779ae4 target/riscv: rvv-1.0: floating-point classify instructions 435b103 target/riscv: rvv-1.0: floating-point square-root instruction bf06171 target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation 19b9951 target/riscv: rvv-1.0: update vext_max_elems() for load/store insns d20f970 target/riscv: rvv-1.0: load/store whole register instructions 5c402cd target/riscv: rvv-1.0: amo operations 4cea576 target/riscv: rvv-1.0: fault-only-first unit stride load df89c58 target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns 757ebcb target/riscv: rvv-1.0: index load and store instructions 1494d82 target/riscv: rvv-1.0: stride load and store instructions 6864fb8 target/riscv: rvv-1.0: configure instructions ee407a9 target/riscv: rvv:1.0: add translation-time nan-box helper function 5f9131d target/riscv: introduce more imm value modes in translator functions 6318158 target/riscv: rvv-1.0: update check functions 25db288 target/riscv: rvv-1.0: add VMA and VTA 1d09441 target/riscv: rvv-1.0: add fractional LMUL e398dae target/riscv: rvv-1.0: remove MLEN calculations ee0f758 target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers 5f3a9fd target/riscv: rvv-1.0: add vlenb register 14eea65 target/riscv: rvv-1.0: add vcsr register fbb24fd target/riscv: rvv-1.0: remove rvv related codes from fcsr registers 8b8837d target/riscv: rvv-1.0: add translation-time vector context status 30b007d target/riscv: rvv-1.0: introduce writable misa.v field 10f5da2 target/riscv: rvv-1.0: add sstatus VS field e9e0096 target/riscv: rvv-1.0: add mstatus VS field 7118b4f target/riscv: Use FIELD_EX32() to extract wd field 6a9f16f target/riscv: drop vector 0.7.1 and add 1.0 support === OUTPUT BEGIN === 1/72 Checking commit 6a9f16fb6790 (target/riscv: drop vector 0.7.1 and add 1.0 support) 2/72 Checking commit 7118b4f8709b (target/riscv: Use FIELD_EX32() to extract wd field) 3/72 Checking commit e9e009618e61 (target/riscv: rvv-1.0: add mstatus VS field) 4/72 Checking commit 10f5da2d835a (target/riscv: rvv-1.0: add sstatus VS field) 5/72 Checking commit 30b007dbf59a (target/riscv: rvv-1.0: introduce writable misa.v field) 6/72 Checking commit 8b8837d8e9ad (target/riscv: rvv-1.0: add translation-time vector context status) WARNING: Block comments use a leading /* on a separate line #440: FILE: target/riscv/translate.c:451: +/* The states of mstatus_vs are: total: 0 errors, 1 warnings, 409 lines checked Patch 6/72 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 7/72 Checking commit fbb24fd9bd43 (target/riscv: rvv-1.0: remove rvv related codes from fcsr registers) 8/72 Checking commit 14eea65cf96c (target/riscv: rvv-1.0: add vcsr register) 9/72 Checking commit 5f3a9fda32dc (target/riscv: rvv-1.0: add vlenb register) 10/72 Checking commit ee0f758f2aaf (target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers) 11/72 Checking commit e398dae337f2 (target/riscv: rvv-1.0: remove MLEN calculations) 12/72 Checking commit 1d094415d77f (target/riscv: rvv-1.0: add fractional LMUL) 13/72 Checking commit 25db288a5551 (target/riscv: rvv-1.0: add VMA and VTA) ERROR: spaces required around that '*' (ctx:WxV) #112: FILE: target/riscv/vector_helper.c:236: + vext_ldst_elem_fn *ldst_elem, ^ total: 1 errors, 0 warnings, 3131 lines checked Patch 13/72 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 14/72 Checking commit 63181582742f (target/riscv: rvv-1.0: update check functions) 15/72 Checking commit 5f9131dda61c (target/riscv: introduce more imm value modes in translator functions) 16/72 Checking commit ee407a9f6343 (target/riscv: rvv:1.0: add translation-time nan-box helper function) 17/72 Checking commit 6864fb863161 (target/riscv: rvv-1.0: configure instructions) 18/72 Checking commit 1494d82cfd3d (target/riscv: rvv-1.0: stride load and store instructions) 19/72 Checking commit 757ebcb4a340 (target/riscv: rvv-1.0: index load and store instructions) 20/72 Checking commit df89c589d699 (target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns) 21/72 Checking commit 4cea576480f2 (target/riscv: rvv-1.0: fault-only-first unit stride load) 22/72 Checking commit 5c402cd18c17 (target/riscv: rvv-1.0: amo operations) 23/72 Checking commit d20f9703ec35 (target/riscv: rvv-1.0: load/store whole register instructions) 24/72 Checking commit 19b9951efce1 (target/riscv: rvv-1.0: update vext_max_elems() for load/store insns) 25/72 Checking commit bf06171f18c7 (target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation) 26/72 Checking commit 435b103c57d3 (target/riscv: rvv-1.0: floating-point square-root instruction) 27/72 Checking commit 7779ae4f55f2 (target/riscv: rvv-1.0: floating-point classify instructions) 28/72 Checking commit 5e71b3fcf9f0 (target/riscv: rvv-1.0: mask population count instruction) 29/72 Checking commit 8466af8a2728 (target/riscv: rvv-1.0: find-first-set mask bit instruction) 30/72 Checking commit 7fb63618bbd9 (target/riscv: rvv-1.0: set-X-first mask bit instructions) 31/72 Checking commit 74692f6ea477 (target/riscv: rvv-1.0: iota instruction) 32/72 Checking commit 9bb22ce18aa8 (target/riscv: rvv-1.0: element index instruction) 33/72 Checking commit 0931fb7adfef (target/riscv: rvv-1.0: allow load element with sign-extended) 34/72 Checking commit f692e274f4a8 (target/riscv: rvv-1.0: register gather instructions) 35/72 Checking commit af81a16ff564 (target/riscv: rvv-1.0: integer scalar move instructions) 36/72 Checking commit 08e812261a85 (target/riscv: rvv-1.0: floating-point move instruction) 37/72 Checking commit 4fe5bbfe3124 (target/riscv: rvv-1.0: floating-point scalar move instructions) 38/72 Checking commit 78f16c195e71 (target/riscv: rvv-1.0: whole register move instructions) 39/72 Checking commit f9c9b41af4c6 (target/riscv: rvv-1.0: integer extension instructions) 40/72 Checking commit 4982bd628afd (target/riscv: rvv-1.0: single-width averaging add and subtract instructions) 41/72 Checking commit 95871592dbac (target/riscv: rvv-1.0: single-width bit shift instructions) 42/72 Checking commit 591bb6ef5968 (target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow) 43/72 Checking commit 9e00723dcdc5 (target/riscv: rvv-1.0: narrowing integer right shift instructions) 44/72 Checking commit 5f4c001eb6d8 (target/riscv: rvv-1.0: widening integer multiply-add instructions) 45/72 Checking commit 64635ad62a71 (target/riscv: rvv-1.0: single-width saturating add and subtract instructions) 46/72 Checking commit 11c0e36258db (target/riscv: rvv-1.0: integer comparison instructions) 47/72 Checking commit c0a16eeb8534 (target/riscv: rvv-1.0: floating-point compare instructions) 48/72 Checking commit 0d96fb83d61f (target/riscv: rvv-1.0: mask-register logical instructions) 49/72 Checking commit ba9b3d7715d2 (target/riscv: rvv-1.0: slide instructions) 50/72 Checking commit 37b1bba99419 (target/riscv: rvv-1.0: floating-point slide instructions) 51/72 Checking commit a54617f8d719 (target/riscv: rvv-1.0: narrowing fixed-point clip instructions) 52/72 Checking commit 6a4392279035 (target/riscv: rvv-1.0: single-width floating-point reduction) 53/72 Checking commit bddb386dcbd7 (target/riscv: rvv-1.0: widening floating-point reduction instructions) 54/72 Checking commit bd98d710c083 (target/riscv: rvv-1.0: single-width scaling shift instructions) 55/72 Checking commit 241debb3c3f1 (target/riscv: rvv-1.0: remove widening saturating scaled multiply-add) 56/72 Checking commit b0e7ad91e1d3 (target/riscv: rvv-1.0: remove vmford.vv and vmford.vf) 57/72 Checking commit 3179608f073f (target/riscv: rvv-1.0: remove integer extract instruction) 58/72 Checking commit 511c21a27f30 (target/riscv: rvv-1.0: floating-point min/max instructions) 59/72 Checking commit 76ffa24ef5fd (target/riscv: introduce floating-point rounding mode enum) 60/72 Checking commit c056e259e192 (target/riscv: rvv-1.0: floating-point/integer type-convert instructions) 61/72 Checking commit 598227108d37 (target/riscv: rvv-1.0: widening floating-point/integer type-convert) 62/72 Checking commit 523b3cc607a3 (target/riscv: add "set round to odd" rounding mode helper function) 63/72 Checking commit 518bc3c4d628 (target/riscv: rvv-1.0: narrowing floating-point/integer type-convert) 64/72 Checking commit d5b6972c65f4 (target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits) 65/72 Checking commit e9df65e8d957 (target/riscv: rvv-1.0: implement vstart CSR) WARNING: Block comments use a leading /* on a separate line #1039: FILE: target/riscv/vector_helper.c:4722: + /* EEW = 8 */ \ total: 0 errors, 1 warnings, 947 lines checked Patch 65/72 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 66/72 Checking commit 81cdec9fb9d9 (target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid) 67/72 Checking commit 3f07b9aab8e5 (target/riscv: rvv-1.0: set mstatus.SD bit when writing vector CSRs) 68/72 Checking commit eb47c134186d (target/riscv: gdb: modify gdb csr xml file to align with csr register map) 69/72 Checking commit e2e0371e6b47 (target/riscv: gdb: support vector registers for rv64 & rv32) 70/72 Checking commit 9a317316cda9 (target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction) 71/72 Checking commit bac292af80a1 (target/riscv: rvv-1.0: floating-point reciprocal estimate instruction) 72/72 Checking commit e79af24b6ea0 (target/riscv: set mstatus.SD bit when writing fp CSRs) === OUTPUT END === Test command exited with code: 1 The full log is available at http://patchew.org/logs/20210112093950.17530-1-frank.ch...@sifive.com/testing.checkpatch/?type=message. --- Email generated automatically by Patchew [https://patchew.org/]. Please send your feedback to patchew-de...@redhat.com
