As reported in https://bugs.launchpad.net/bugs/1905356
Changes for v3:
* Move TBFLAG_{A64,A32,M32,AM32} to tb->cs_base, leaving only
TBFLAG_ANY in tb->flags. This solves our current problem of
running out of bits in tb->flags.
* Dropped "Enforce alignment for sve unpredicated LDR/STR";
there are more changes required for SVE, and I think I'll
integrate those into my SVE2 patch set.
Changes for v2:
* Rearranged things a bit, which has made it easy to support
SCTLR.A/CCR.UNALIGN_TRAP. At least for non-sve code, where
we issue tcg load/store operations. Predicated sve load/stores
will require more work within the helpers.
r~
Richard Henderson (30):
target/arm: Fix decode of align in VLDST_single
target/arm: Rename TBFLAG_A32, SCTLR_B
target/arm: Rename TBFLAG_ANY, PSTATE_SS
target/arm: Add wrapper macros for accessing tbflags
target/arm: Introduce CPUARMTBFlags
target/arm: Move mode specific TB flags to tb->cs_base
target/arm: Move TBFLAG_AM32 bits to the top
target/arm: Move TBFLAG_ANY bits to the bottom
target/arm: Add ALIGN_MEM to TBFLAG_ANY
target/arm: Adjust gen_aa32_{ld,st}_i32 for align+endianness
target/arm: Merge gen_aa32_frob64 into gen_aa32_ld_i64
target/arm: Fix SCTLR_B test for TCGv_i64 load/store
target/arm: Adjust gen_aa32_{ld,st}_i64 for align+endianness
target/arm: Enforce word alignment for LDRD/STRD
target/arm: Enforce alignment for LDA/LDAH/STL/STLH
target/arm: Enforce alignment for LDM/STM
target/arm: Enforce alignment for RFE
target/arm: Enforce alignment for SRS
target/arm: Enforce alignment for VLDM/VSTM
target/arm: Enforce alignment for VLDR/VSTR
target/arm: Enforce alignment for VLDn (all lanes)
target/arm: Enforce alignment for VLDn/VSTn (multiple)
target/arm: Enforce alignment for VLDn/VSTn (single)
target/arm: Use finalize_memop for aa64 gpr load/store
target/arm: Use finalize_memop for aa64 fpr load/store
target/arm: Enforce alignment for aa64 load-acq/store-rel
target/arm: Use MemOp for size + endian in aa64 vector ld/st
target/arm: Enforce alignment for aa64 vector LDn/STn (multiple)
target/arm: Enforce alignment for aa64 vector LDn/STn (single)
target/arm: Enforce alignment for sve LD1R
target/arm/cpu.h | 105 ++++++++-----
target/arm/translate.h | 38 +++++
target/arm/neon-ls.decode | 4 +-
target/arm/helper-a64.c | 2 +-
target/arm/helper.c | 160 +++++++++++---------
target/arm/translate-a64.c | 214 +++++++++++++-------------
target/arm/translate-sve.c | 2 +-
target/arm/translate.c | 258 +++++++++++++++++---------------
target/arm/translate-neon.c.inc | 117 ++++++++++++---
target/arm/translate-vfp.c.inc | 20 +--
10 files changed, 555 insertions(+), 365 deletions(-)
--
2.25.1
