On Thu, 10 Dec 2020 at 14:16, Philippe Mathieu-Daudé <f4...@amsat.org> wrote:
>
> Malicious user can set the feedback divisor for the PLLs
> to zero, triggering a floating-point exception (SIGFPE).
>
> As the datasheet [*] is not clear how hardware behaves
> when these bits are zeroes, use the maximum divisor
> possible (128) to avoid the software FPE.
>
> [*] Zynq-7000 TRM, UG585 (v1.12.2)
> B.28 System Level Control Registers (slcr)
> -> "Register (slcr) ARM_PLL_CTRL"
> 25.10.4 PLLs
> -> "Software-Controlled PLL Update"
>
> Fixes: 38867cb7ec9 ("hw/misc/zynq_slcr: add clock generation for uarts")
> Reported-by: Gaoning Pan <p...@zju.edu.cn>
> Signed-off-by: Philippe Mathieu-Daudé <f4...@amsat.org>
Applied to target-arm.next, thanks.
-- PMM
