The RISC-V QEMU port currently has lot of preprocessor directives that check if we are targetting a 32-bit or 64-bit CPU. This means that the 64-bit RISC-V target can not run 32-bit CPUs. This is different to most other QEMU architectures and doesn't allow us to mix xlens (such as when running Hypervisors with different xlen guests). This series is a step toward removing some of those to allow us to use 32-bit CPUs on 64-bit RISC-V targets. v2: - Rebase on the latest RISC-V tree
Alistair Francis (15): hw/riscv: Expand the is 32-bit check to support more CPUs target/riscv: Add a TYPE_RISCV_CPU_BASE CPU riscv: spike: Remove target macro conditionals riscv: virt: Remove target macro conditionals hw/riscv: boot: Remove compile time XLEN checks hw/riscv: virt: Remove compile time XLEN checks hw/riscv: spike: Remove compile time XLEN checks hw/riscv: sifive_u: Remove compile time XLEN checks target/riscv: fpu_helper: Match function defs in HELPER macros target/riscv: Add a riscv_cpu_is_32bit() helper function target/riscv: Specify the XLEN for CPUs target/riscv: cpu: Remove compile time XLEN checks target/riscv: cpu_helper: Remove compile time XLEN checks target/riscv: csr: Remove compile time XLEN checks target/riscv: cpu: Set XLEN independently from target include/hw/riscv/boot.h | 8 +- include/hw/riscv/spike.h | 6 -- include/hw/riscv/virt.h | 6 -- target/riscv/cpu.h | 8 ++ target/riscv/cpu_bits.h | 4 +- hw/riscv/boot.c | 69 +++++++++------ hw/riscv/sifive_u.c | 57 ++++++------ hw/riscv/spike.c | 50 ++++++----- hw/riscv/virt.c | 36 ++++---- target/riscv/cpu.c | 84 ++++++++++++------ target/riscv/cpu_helper.c | 12 +-- target/riscv/csr.c | 182 ++++++++++++++++++++------------------ target/riscv/fpu_helper.c | 16 ++-- 13 files changed, 302 insertions(+), 236 deletions(-) -- 2.29.2
