Add more IRQ lines. Depends on ACPI.
Also enable this only with userspace ioapic,
not sure whenever the kernel can handle two ioapics.
Signed-off-by: Gerd Hoffmann <kra...@redhat.com>
---
include/hw/i386/ioapic_internal.h | 2 +-
include/hw/i386/x86.h | 1 +
hw/i386/acpi-common.c | 10 ++++++++++
hw/i386/microvm.c | 30 ++++++++++++++++++++++++++++--
4 files changed, 40 insertions(+), 3 deletions(-)
diff --git a/include/hw/i386/ioapic_internal.h
b/include/hw/i386/ioapic_internal.h
index 0ac9e2400d6b..4cebd2e32c9f 100644
--- a/include/hw/i386/ioapic_internal.h
+++ b/include/hw/i386/ioapic_internal.h
@@ -27,7 +27,7 @@
#include "qemu/notify.h"
#include "qom/object.h"
-#define MAX_IOAPICS 1
+#define MAX_IOAPICS 2
#define IOAPIC_LVT_DEST_SHIFT 56
#define IOAPIC_LVT_DEST_IDX_SHIFT 48
diff --git a/include/hw/i386/x86.h b/include/hw/i386/x86.h
index bfa9cb2a258b..6da57033a875 100644
--- a/include/hw/i386/x86.h
+++ b/include/hw/i386/x86.h
@@ -120,6 +120,7 @@ bool x86_machine_is_acpi_enabled(const X86MachineState
*x86ms);
typedef struct GSIState {
qemu_irq i8259_irq[ISA_NUM_IRQS];
qemu_irq ioapic_irq[IOAPIC_NUM_PINS];
+ qemu_irq ioapic2_irq[IOAPIC_NUM_PINS];
} GSIState;
qemu_irq x86_allocate_cpu_irq(void);
diff --git a/hw/i386/acpi-common.c b/hw/i386/acpi-common.c
index 8a769654060e..f0689392a39f 100644
--- a/hw/i386/acpi-common.c
+++ b/hw/i386/acpi-common.c
@@ -103,6 +103,16 @@ void acpi_build_madt(GArray *table_data, BIOSLinker
*linker,
io_apic->address = cpu_to_le32(IO_APIC_DEFAULT_ADDRESS);
io_apic->interrupt = cpu_to_le32(0);
+ if (object_property_find(OBJECT(x86ms), "ioapic2")) {
+ AcpiMadtIoApic *io_apic2;
+ io_apic2 = acpi_data_push(table_data, sizeof *io_apic);
+ io_apic2->type = ACPI_APIC_IO;
+ io_apic2->length = sizeof(*io_apic);
+ io_apic2->io_apic_id = ACPI_BUILD_IOAPIC_ID + 1;
+ io_apic2->address = cpu_to_le32(IO_APIC_DEFAULT_ADDRESS + 0x10000);
+ io_apic2->interrupt = cpu_to_le32(24);
+ }
+
if (x86ms->apic_xrupt_override) {
intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
diff --git a/hw/i386/microvm.c b/hw/i386/microvm.c
index 638e95c39e8c..15c3e078a4aa 100644
--- a/hw/i386/microvm.c
+++ b/hw/i386/microvm.c
@@ -99,7 +99,11 @@ static void microvm_gsi_handler(void *opaque, int n, int
level)
{
GSIState *s = opaque;
- qemu_set_irq(s->ioapic_irq[n], level);
+ if (n >= 24) {
+ qemu_set_irq(s->ioapic2_irq[n - 24], level);
+ } else {
+ qemu_set_irq(s->ioapic_irq[n], level);
+ }
}
static void create_gpex(MicrovmMachineState *mms)
@@ -157,6 +161,7 @@ static void microvm_devices_init(MicrovmMachineState *mms)
ISABus *isa_bus;
ISADevice *rtc_state;
GSIState *gsi_state;
+ bool ioapic2 = false;
int i;
/* Core components */
@@ -165,8 +170,13 @@ static void microvm_devices_init(MicrovmMachineState *mms)
if (mms->pic == ON_OFF_AUTO_ON || mms->pic == ON_OFF_AUTO_AUTO) {
x86ms->gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS);
} else {
+ int pins = GSI_NUM_PINS;
+ if (!kvm_ioapic_in_kernel() && x86_machine_is_acpi_enabled(x86ms)) {
+ ioapic2 = true;
+ pins += 24;
+ }
x86ms->gsi = qemu_allocate_irqs(microvm_gsi_handler,
- gsi_state, GSI_NUM_PINS);
+ gsi_state, pins);
}
isa_bus = isa_bus_new(NULL, get_system_memory(), get_system_io(),
@@ -175,6 +185,22 @@ static void microvm_devices_init(MicrovmMachineState *mms)
ioapic_init_gsi(gsi_state, "machine");
+ if (ioapic2) {
+ DeviceState *dev;
+ SysBusDevice *d;
+ unsigned int i;
+
+ dev = qdev_new(TYPE_IOAPIC);
+ object_property_add_child(OBJECT(mms), "ioapic2", OBJECT(dev));
+ d = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(d, &error_fatal);
+ sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS + 0x10000);
+
+ for (i = 0; i < IOAPIC_NUM_PINS; i++) {
+ gsi_state->ioapic2_irq[i] = qdev_get_gpio_in(dev, i);
+ }
+ }
+
kvmclock_create(true);
mms->virtio_irq_base = 5;
--
2.27.0
