> -----Original Message----- > From: Alistair Francis [mailto:alistai...@gmail.com] > Sent: Thursday, October 15, 2020 3:12 AM > To: Richard Henderson <richard.hender...@linaro.org> > Cc: Jiangyifei <jiangyi...@huawei.com>; qemu-devel@nongnu.org; > qemu-ri...@nongnu.org; Zhanghailiang <zhang.zhanghaili...@huawei.com>; > sag...@eecs.berkeley.edu; kbast...@mail.uni-paderborn.de; Zhangxiaofeng > (F) <victor.zhangxiaof...@huawei.com>; alistair.fran...@wdc.com; yinyipeng > <yinyipe...@huawei.com>; pal...@dabbelt.com; Wubin (H) > <wu.wu...@huawei.com>; dengkai (A) <dengk...@huawei.com> > Subject: Re: [PATCH V2 1/5] target/riscv: Add basic vmstate description of CPU > > On Wed, Oct 14, 2020 at 8:45 AM Richard Henderson > <richard.hender...@linaro.org> wrote: > > > > On 10/14/20 3:21 AM, Jiangyifei wrote: > > >> Would this be a good time to expand mstatus to uint64_t instead of > > >> target_ulong so that it can be saved as one unit and reduce some > > >> ifdefs in the code base? > > >> > > >> Similarly with some of the other status registers that are two > > >> halved for riscv32. > > > > > > I agree with you that it should be rearranged. > > > But I hope this series will focus on achieving migration. > > > Can I send another patch to rearrange it later? > > > > Well, that changes the bit layout for migration. > > While we could bump the version number, it seemed easier to change the > > representation first. > > +1 it would be great to consolidate these. > > Alistair >
OK. I will change this in the next series. Yifei > > > > > > r~ > >
