On Thu, Sep 24, 2020 at 05:14:06AM -0400, Igor Mammedov wrote: > Spec[1] defines 0 - 3 level memory side cache, however QEMU > CLI allows to specify an intermediate cache level without > specifying previous level. Such option(s) silently ignored > when building HMAT table, which leads to incomplete cache > information. > Make sure that previous level exists and error out > if it hasn't been provided. > > 1) ACPI 6.2A 5.2.27.5 Memory Side Cache Information Structure > > Fixes: https://bugzilla.redhat.com/show_bug.cgi?id=1842877 > Signed-off-by: Igor Mammedov <imamm...@redhat.com>
Reviewed-by: Eduardo Habkost <ehabk...@redhat.com> Queueing on machine-next, thanks! -- Eduardo
