The following changes since commit 64f0ad8ad8e13257e7c912df470d46784b55c3fd:
Merge remote-tracking branch 'remotes/armbru/tags/pull-error-2020-07-02' into
staging (2020-07-02 15:54:09 +0100)
are available in the Git repository at:
g...@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20200702-1
for you to fetch changes up to 6bf91617f47c74efc99ef48236765d9677c0898e:
target/riscv: configure and turn on vector extension from command line
(2020-07-02 09:19:34 -0700)
----------------------------------------------------------------
This PR contains two patches to improve PLIC support in QEMU.
It also contains one patch that fixes CLINT accesses for RISC-V. This
fixes a regression for most RISC-V boards.
The rest of the PR is adding support for the v0.7.1 RISC-V vector
extensions. This is experimental support as the vector extensions are
still in a draft state.
This is a v2 pull request that has fixed the building on big endian
machines failure.
----------------------------------------------------------------
Alistair Francis (1):
hw/riscv: Allow 64 bit access to SiFive CLINT
Jessica Clarke (2):
riscv: plic: Honour source priorities
riscv: plic: Add a couple of mising sifive_plic_update calls
LIU Zhiwei (61):
target/riscv: add vector extension field in CPURISCVState
target/riscv: implementation-defined constant parameters
target/riscv: support vector extension csr
target/riscv: add vector configure instruction
target/riscv: add an internals.h header
target/riscv: add vector stride load and store instructions
target/riscv: add vector index load and store instructions
target/riscv: add fault-only-first unit stride load
target/riscv: add vector amo operations
target/riscv: vector single-width integer add and subtract
target/riscv: vector widening integer add and subtract
target/riscv: vector integer add-with-carry / subtract-with-borrow
instructions
target/riscv: vector bitwise logical instructions
target/riscv: vector single-width bit shift instructions
target/riscv: vector narrowing integer right shift instructions
target/riscv: vector integer comparison instructions
target/riscv: vector integer min/max instructions
target/riscv: vector single-width integer multiply instructions
target/riscv: vector integer divide instructions
target/riscv: vector widening integer multiply instructions
target/riscv: vector single-width integer multiply-add instructions
target/riscv: vector widening integer multiply-add instructions
target/riscv: vector integer merge and move instructions
target/riscv: vector single-width saturating add and subtract
target/riscv: vector single-width averaging add and subtract
target/riscv: vector single-width fractional multiply with rounding and
saturation
target/riscv: vector widening saturating scaled multiply-add
target/riscv: vector single-width scaling shift instructions
target/riscv: vector narrowing fixed-point clip instructions
target/riscv: vector single-width floating-point add/subtract instructions
target/riscv: vector widening floating-point add/subtract instructions
target/riscv: vector single-width floating-point multiply/divide
instructions
target/riscv: vector widening floating-point multiply
target/riscv: vector single-width floating-point fused multiply-add
instructions
target/riscv: vector widening floating-point fused multiply-add
instructions
target/riscv: vector floating-point square-root instruction
target/riscv: vector floating-point min/max instructions
target/riscv: vector floating-point sign-injection instructions
target/riscv: vector floating-point compare instructions
target/riscv: vector floating-point classify instructions
target/riscv: vector floating-point merge instructions
target/riscv: vector floating-point/integer type-convert instructions
target/riscv: widening floating-point/integer type-convert instructions
target/riscv: narrowing floating-point/integer type-convert instructions
target/riscv: vector single-width integer reduction instructions
target/riscv: vector wideing integer reduction instructions
target/riscv: vector single-width floating-point reduction instructions
target/riscv: vector widening floating-point reduction instructions
target/riscv: vector mask-register logical instructions
target/riscv: vector mask population count vmpopc
target/riscv: vmfirst find-first-set mask bit
target/riscv: set-X-first mask bit
target/riscv: vector iota instruction
target/riscv: vector element index instruction
target/riscv: integer extract instruction
target/riscv: integer scalar move instruction
target/riscv: floating-point scalar move instructions
target/riscv: vector slide instructions
target/riscv: vector register gather instruction
target/riscv: vector compress instruction
target/riscv: configure and turn on vector extension from command line
target/riscv/cpu.h | 82 +-
target/riscv/cpu_bits.h | 15 +
target/riscv/helper.h | 1069 +++++++
target/riscv/internals.h | 41 +
target/riscv/insn32-64.decode | 11 +
target/riscv/insn32.decode | 372 +++
hw/riscv/sifive_clint.c | 2 +-
hw/riscv/sifive_plic.c | 20 +-
target/riscv/cpu.c | 50 +
target/riscv/csr.c | 75 +-
target/riscv/fpu_helper.c | 33 +-
target/riscv/insn_trans/trans_rvv.inc.c | 2888 ++++++++++++++++++
target/riscv/translate.c | 27 +-
target/riscv/vector_helper.c | 4899 +++++++++++++++++++++++++++++++
target/riscv/Makefile.objs | 2 +-
15 files changed, 9535 insertions(+), 51 deletions(-)
create mode 100644 target/riscv/internals.h
create mode 100644 target/riscv/insn_trans/trans_rvv.inc.c
create mode 100644 target/riscv/vector_helper.c
