As this function will be used by fcvt.d.s in trans_rvd.inc.c,
make it a visible function for RVF and RVD.
Signed-off-by: LIU Zhiwei <zhiwei_...@c-sky.com>
---
target/riscv/insn_trans/trans_rvf.inc.c | 14 --------------
target/riscv/translate.c | 14 ++++++++++++++
2 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvf.inc.c
b/target/riscv/insn_trans/trans_rvf.inc.c
index 3bfd8881e7..0d5ce373cb 100644
--- a/target/riscv/insn_trans/trans_rvf.inc.c
+++ b/target/riscv/insn_trans/trans_rvf.inc.c
@@ -23,20 +23,6 @@
return false; \
} while (0)
-/*
- * RISC-V requires NaN-boxing of narrower width floating
- * point values. This applies when a 32-bit value is
- * assigned to a 64-bit FP register. Thus this does not
- * apply when the RVD extension is not present.
- */
-static void gen_nanbox_fpr(DisasContext *ctx, int regno)
-{
- if (has_ext(ctx, RVD)) {
- tcg_gen_ori_i64(cpu_fpr[regno], cpu_fpr[regno],
- MAKE_64BIT_MASK(32, 32));
- }
-}
-
static bool trans_flw(DisasContext *ctx, arg_flw *a)
{
TCGv t0 = tcg_temp_new();
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 9632e79cf3..4b1534c9a6 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -90,6 +90,20 @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext)
return ctx->misa & ext;
}
+/*
+ * RISC-V requires NaN-boxing of narrower width floating
+ * point values. This applies when a 32-bit value is
+ * assigned to a 64-bit FP register. Thus this does not
+ * apply when the RVD extension is not present.
+ */
+static void gen_nanbox_fpr(DisasContext *ctx, int regno)
+{
+ if (has_ext(ctx, RVD)) {
+ tcg_gen_ori_i64(cpu_fpr[regno], cpu_fpr[regno],
+ MAKE_64BIT_MASK(32, 32));
+ }
+}
+
static void generate_exception(DisasContext *ctx, int excp)
{
tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
--
2.23.0
